用74HC163设计余3码计数器(结构描述)

题目：用VHDL层次结构设计方法设计程序并仿真（时序），底层器件是74HC163。

 

  1 library ieee;         --第一个底层设计实体 nand_gate
  2 use ieee.std_logic_1164.all;
  3 entity nand_gate is
  4 port( op1 , op2 : in std_logic;     --nand_gate的两个数据输入端
  5     nand_result : out std_logic);  --nand_gate的数据输出端口
  6 end nand_gate;
  7 architecture behave of nand_gate is
  8 begin
  9     nand_result <= not (op1 and op2);  --nand_gate 的功能
 10 end behave;
 11 
 12 library ieee;        --第二个底层设计实体 not_gate
 13 use ieee.std_logic_1164.all;
 14 entity not_gate is
 15 port(           op : in std_logic;  --not_gate 的数据输入端
 16         not_result : out std_logic);  --not_gate的数据输出端口
 17 end not_gate;
 18 architecture behave of not_gate is
 19 begin
 20     not_result <= not op;      --not_gate 的功能
 21 end behave;
 22 
 23 library ieee;   --第三个底层设计实体
 24 use ieee.std_logic_1164.all;
 25 entity and_gate is
 26 port( op1 , op2 : in std_logic;   --and_gate 的数据输入端
 27      and_result : out std_logic);   --and_gate的数据输出端口
 28 end and_gate;
 29 architecture behave of and_gate is
 30 begin
 31     and_result <= op1 and op2;    --and_gate 的功能
 32 end behave;
 33 
 34 library ieee;               --第四个底层设计实体 74HC163
 35 use ieee.std_logic_1164.all;
 36 use ieee.std_logic_arith.all;
 37 entity counter74163 is
 38 port (ep , et , clk , ld , rd : in std_logic;  --控制端 et、ep，时钟信号clk，置数ld，复位rd
 39                             d : in unsigned(3 downto 0);    --数据输入端
 40                             q : out unsigned(3 downto 0);  --数据输出端
 41                             c : buffer std_logic);   --进位输出
 42 end counter74163;
 43 architecture behave of counter74163 is
 44 signal iq : unsigned(3 downto 0);
 45 begin
 46 process(clk , ld , rd , ep , et , iq , d)
 47 begin
 48     if(iq = 0) then iq <= d;
 49     elsif(clk'event and clk = '1') then
 50         if(rd = '0') then iq <= (others => '0');   --同步清零
 51         elsif(ld = '0') then iq <= d;             --同步置数
 52         elsif c = '1' then iq <= d;              --计数满，回d
 53         elsif (ep and et) = '1' then iq <= iq + 1;  --计数
 54         end if;
 55     end if;
 56     if(iq = 0) then iq <= d;
 57     elsif(iq = 13) and (et = '1') then c <= '1';    --产生进位输出
 58     else c <= '0';
 59     end if;
 60     q <= iq;
 61 end process;
 62 end behave;
 63 
 64 library ieee;            --程序包
 65 use ieee.std_logic_1164.all;
 66 use ieee.std_logic_arith.all;
 67 package lowgate_components is
 68 component nand_gate       --说明原件与非门
 69     port( op1 , op2 : in std_logic;
 70         nand_result : out std_logic);
 71 end component;
 72 component not_gate    --说明原件非门
 73     port(       op : in std_logic;
 74          not_result : out std_logic);
 75 end component;
 76 component and_gate  --说明原件与门
 77     port( op1 , op2 : in std_logic;   
 78           and_result : out std_logic);
 79 end component;
 80 component counter74163    --说明原件74HC163
 81     port(ep , et , clk , ld , rd : in std_logic;
 82                             d    : in unsigned(3 downto 0);
 83                             q    : out unsigned(3 downto 0);
 84                             c    : buffer std_logic);
 85 end component;
 86 end lowgate_components;
 87 
 88 
 89 library ieee;     --顶层设计实体
 90 use ieee.std_logic_1164.all;
 91 use ieee.std_logic_arith.all;
 92 use work.lowgate_components.all;
 93 entity counter_excess_3_code is
 94 port(Clk, Ep, Et, Ld : in std_logic;             --时钟信号，控制端，置数端
 95     D    : in unsigned(3 downto 0);    --数据输入端
 96     Iq   : buffer unsigned(3 downto 0);   --数据输出端
 97     rco  : out std_logic);       --进位输出端口
 98 end counter_excess_3_code;
 99 architecture behave of counter_excess_3_code is
100 signal b3 , b4: std_logic;
101 begin
102 G1 : counter74163 port map      --对74HC163的一次例化
103         (et => Et , ep => Ep , clk => Clk , ld => b4 , rd => '1',
104         d => D , q => Iq);
105 G2 : nand_gate port map    --对于非门的一次例化
106         (op1 => Iq(3) , op2 => Iq(2) , nand_result => b3);
107 G3 : not_gate port map      --对非门的一次例化
108         (op => b3 , not_result => rco);
109 G4 : and_gate port map   --对与门的一次例化2
110         (op1 => b3 , op2 => Ld , and_result => b4);
111 end behave;
112     

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