【FPGA学习笔记】VHDL学习（六）用VHDL描述基本逻辑电路

一、组合逻辑电路

组合逻辑电路包括门电路，三态门电路，总线缓冲器，编码器，译码器，多路数据选择器，多路数据分配器。
1、门电路：与非，或非，亦或
有两种描述方法：逻辑运算符和真值表描述方法。

--门电路设计
--逻辑运算符描述方法
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY gate IS
	PORT(a,b : IN STD_LOGIC;
		Ynand,Ynor,Yxor : OUT STD_LOGIC);
END gate;

ARCHITECTURE one OF gate IS
BEGIN
	Ynand <= a NAND b;
	Ynor  <= a NOR  b;
	Yxor <= a XOR b;
END one;

--真值表描述
ARCHITECTURE two OF gate IS
	SIGNAL s : STD_LOGIC_VECTOR(1 TO 0);
BEGIN 
	s = a & b;
	PROCESS(s)
	BEGIN
		CASE s IS
			WHEN "00"=> Ynand <='1';Ynor <= '1';Yxor <= '0';
			WHEN "01"=> Ynand <='1';Ynor <= '0';Yxor <= '1';
			WHEN "10"=> Ynand <='1';Ynor <= '0';Yxor <= '1';
			WHEN "11"=> Ynand <='0';Ynor <= '0';Yxor <= '0';
			WHEN OTHERS => Ynand <='0';Ynor <= '0';Yxor => '0';
		END CASE;
	END PROCESS;
END two;

2、三态门
当使能信号“en”为1时，导通；当“en”为1时，输出为高阻态Z。

--三态门电路
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_state IS
	PORT(din,en : IN STD_LOGIC;
		dout :OUT STD_LOGIC);
END tri_state;
ARCHITECTURE rtl OF tri_state IS
BEGIN
	PROCESS(en,din)
		IF (en = '1')THEN
			dout <= din;
		ELSE
			dout <= 'z';
		END IF;
	END PROCESS;
END rtl;

3、数据缓冲器

微机的总线驱动中经常用到单向数据缓冲器，用于驱动地址总线和控制总线。
当“en”为1时，输出输出等于输入，否则为高阻态。

--8位单向数据缓冲器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_buffer IS
	PORT (din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		   en : IN STD_LOGIC;
		  dout：OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
END tri_buffer;

ARCHITECTURE rtl OF tri_buffer IS
BEGIN
	PROCESS(en,din)
		IF(en = '1')THEN
			dout <= din;
		ELSE
			dout <= "zzzzzzzz";
		END IF;
	END PROCESS;
END rtl;

双向数据缓冲器：用于数据总线的驱动和缓冲。
有两个数据传递方向：a->b,b->a。

--8位双向数据缓冲器
LIBRARY IEEE；
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bi_dir IS
	PORT(en,dr :IN STD_LOGIC;
		a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END bi_dir;
ARCHITECTURE rtl OF bi_dir IS
	SIGNAL Aout,Bout : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	one : PROCESS(a,en,dr)
	BEGIN
		IF en = '0' AND dr = '0' THEN 
			Bout <= a;
		ELSE
			Bout <= 'ZZZZZZZZ';
		END IF;
			b = Bout
	END PROCESS;

	two : PROCESS(b,en,dr)
	BEGIN
		IF en = '0' AND dr = '1' THEN 
			Aout <= b;
		ELSE
			Aout <= 'ZZZZZZZZ';
		END IF;
			a = Aout;
	END PROCESS;
END rtl;

4、编码器、译码器

编码器，if语句具有优先性，谁在外层谁优先。

-- 8-3线优先编码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY encoder IS
	PORT(i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		y  ;OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END encoder;

ARCHITECTURE rtl OF encoder IS

BEGIN
	PROCESS (i)
	BEGIN
		IF 
		i(7) = '1' THEN  y <= "111";
		ELSIF i(6) = '1' THEN y <= "110";
		ELSIF i(5) = '1' THEN y <= "101";
		ELSIF i(4) = '1' THEN y <= "100";
		ELSIF i(3) = '1' THEN y <= "011";
		ELSIF i(2) = '1' THEN y <= "010";
		ELSIF i(1) = '1' THEN y <= "001";
		ELSIF i(0) = '1' THEN y <= "000";
		END IF;
	END PROCESS;
END rtl;

3-8译码器，输出端低电平有效。
g1,g2,g3为使能端，当g1为1时，输出全为1，

--3-8译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder IS
	PORT(a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
		 g1,g2,g3 : IN STD_LOGIC;
		 y : OUT STD_LOGIC(7 DOWNTO 0));
END decoder;
ARCHITECTURE rtl OF decoder IS
BEGIN
	PROCESS(a,g1,g2,g3)
		IF g1 = '0' THEN
			y <= '11111111';
		ELSIF g2 = '1' OR g3 = '1'THEN
			y <= '11111111';
		ELSE
			CASE a IS
				WHEN "000"=> y<="11111110";
				WHEN "001"=> y<="11111101";
				WHEN "010"=> y<="11111011";
				WHEN "011"=> y<="11110111";
				WHEN "100"=> y<="11101111";
				WHEN "101"=> y<="11011111";
				WHEN "110"=> y<="10111111";
				WHEN "111"=> y<="01111111";
			END CASE;
		END IF;
	END PROCESS;
END rtl;

5、数据选择器、数据分配器

--四选一数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_1 IS
	PORT(a : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		d0,d1,d2,d3 : IN STD_LOGIC;
		g : IN STD_LOGIC;
		y : OUT STD_LOGIC);
END mux4_1;

ARCHITECTURE rtl OF mux4_1 IS
BEGIN 
	PROCESS(a,g,d1,d2,d3,d0)
	BEGIN
		IF(g = 0 )  THEN y <= '0';
		ELSE
			CASE a IS
				WHEN "00" => y <= d0;
				WHEN "01" => y <= d1;
				WHEN "10" => y <= d2;
				WHEN "11" => y <= d3;
				WHEN OTHERS => y <= '1';
				END CASE;
		END IF;
	END PROCESS;
END rtl;

--1-4数据分配器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY demux1_4 IS
	PORT(din : IN STD_LOGIC;
		a :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		y0,y1,y2,y3 : OUT STD_LOGIC);
END demux1_4;

ARCHITECTURE rtl OF demux1_4 IS
BEGIN
	PROCESS (din,a)
	BEGIN	
		y0 <= '0';y1 <= '0';y2 <= '0';y3 <= '0';
		CASE a IS
			WHEN "00"=> y0 <= din;
			WHEN "01"=> y1 <= din;
			WHEN "10"=> y2 <= din;
			WHEN "11"=> y3 <= din;
		END CASE;
	END PROCESS;
END rtl;