DDR（五）DDR2初始化顺序

现在网上的S5PV210的u-boot源码中关于内存的初始化过程，基本上我没有找到任何资料有过分析DDR2的内存初始化代码的。在看u-boot的这段代码时，也徘徊了很久，不知道如下手，很多文章或资料都将这一段分析过程有意无意的隐藏掉了，最多也只是提一下说参考裸板的代码，在找不到任何资料的情况下，我只能依靠芯片手册上，三星在内存控制器这一章，写的关于DDR2的初始化顺序的28个步骤来一条一条去读去看，在安静下来看了芯片手册以后，我发现三星给的裸板的DDR初始化代码和芯片手册上的初始化步骤完全一致，有的时候，最好的资料其实就在手边，只是我一直在想着找捷径，学习哪有那么多捷径？

现在开始关注一下芯片手册上关于DDR2的初始化流程，P598页：

1.查看芯片手册DDR2的初始化顺序
Initialization sequence for DDR2 memory type
1.  To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_incbit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_onbit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetcbit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.  
5. Set the ConControl. At this moment, an auto refresh counter should be off.  
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfigand PwrdnConfigregisters.
9. Set the TimingAref, TimingRow, TimingDataand TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15and QosConfig0~15registers.
11. Wait for thePhyStatus0.ctrl_lockedbit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amountcaused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set thePhyControl0.ctrl_forcebit-field to correct value according to thePhyStatus0.ctrl_lock_value[9:2]bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOPcommand using the DirectCmdregister to assert and to hold CKE to a logic high level.
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refreshcommands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControlto turn on an auto refresh counter.
28. If power down modes is required, set the MemControl registers.

译文如下：
1. 提供稳压电源给内存控制器和内存芯片，内存控制器必须保持CLE在低电平，此时就会提供稳压电源。注：当CKE引脚为低电平时，XDDR2SEL应该处于高电平
2. 依照时钟频率正确配置PhyControl0.ctrl_start_point和PhyControl0.ctrl_incbit-fields的值。配置的PhyControl0.ctrl_dll_on值为'1'以打开PHY DLL。
3. DQS Cleaning：依照时钟频率和内存的tAC参数正确设置PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetcbit-fields位的值。
4. 配置PhyControl0.ctrl_start位的值为'1'
5. 配置ConControl，与此同时，auto refresh自动刷新计数器应该关闭
6. 配置MemControl，与此同时，所有的power down（休眠模式）应该闭关
7. 配置MemConfig0寄存器。如果有两组内存芯片(比如有8片DDR，这8片DDR是分别挂在Memory Port1和Memory Port2上)，再配置MemConfig1寄存器。
8. 配置PrechConfig和PwrdnConfig寄存器
9. 依照内存的tAC参数配置TimingAref, TimingRow, TimingData和TimingPower寄存器
10. 如果需要QoS标准，配置QosControl0~15和QosConfig0~15r寄存器
11. 等待PhyStatus0.ctrl_locked位变为'1'。检查是否PHY DLL是否已锁
12. PHY DLL补偿在内存操作时由PVT(Process, Voltage and Temperature，处理器、电压和温度)变化引起的延迟量。但是，PHY DLL不能因某些可靠的内存操作而切断，除非是工作在低频率下。如果关闭PHY DLL，依照PhyStatus0.ctrl_lock_value[9:2]位的值正确配置PhyControl0.ctrl_force位的值来弥补延迟量(fix delay amount)。清除PhyControl0.ctrl_dll_on位的值来关闭PHY DLL。
13. 上电后，确定最小值为200us的稳定时钟是否发出
14. 使用DirectCmd寄存器发出一个NOP命令，保证CKE引脚为高电平
15. 等最小400ns
16. 使用DirectCmd寄存器发出一个PALL命令
17. 使用DirectCmd寄存器发出一个EMRS2命令，program操作参数
18. 使用DirectCmd寄存器发出一个EMRS3命令，program操作参数
19. 使用DirectCmd寄存器发出一个EMRS命令来使能内存DLLs
20. 使用DirectCmd寄存器发出一个MRS命令，重启内存DLL
21. 使用DirectCmd寄存器发出一个PALL命令
22. 使用DirectCmd寄存器发出两个Auto Refresh(自动刷新)命令
23. 使用DirectCmd寄存器发出一个MRS命令，program操作参数，不要重启内存DLL
24. 等待最小200时钟周期
25. 使用DirectCmd寄存器发出一个EMRS命令给程序的运行参数。如果OCD校正(Off-Chip Driver，片外驱动调校)没有使用，改善一个EMRS命令去设置OCD校准的默认值。在此之后，发送一个EMRS指令去退出OCD校准模式，继续program操作参数
26. 如果有两组DDR芯片，重复14-25步配置chip1的内存，刚刚配置的是chip0，也就是第一组内存芯片
27. 配置ConControlto来打开自动刷新计数器
28. 如果需要power down(休眠)模式，配置MemControl寄存器.

知道了上面的这些初始化步骤，现在再去看三星给的裸板代码中关于SDRAM的BL1的代码，就比较清楚了。