FPGA记录一：Mearly型与Moore型状态机（序列检测案例分析）

一.理论

Mearly型：输出由当前状态和输入共同决定
Moore型：输出只与当前状态有关

ps:状态跳转均与输入和当前状态有关

二.代码区别

2.1Mearly型输出：

always@(posedge sclk or negedge rst_n)
		if(!rst_n)
			c_out <= 1'b0;
		else if(state == S4 && c_in == 1'b0)
			c_out <= 1'b1;
		else
			c_out <= 1'b0;

Modelsim仿真结果：检测到10010序列立刻输出检测信号c_out

2.2Moore型输出：

always@(posedge sclk or negedge rst_n)
		if(!rst_n)
			c_out <= 1'b0;
		else if(state == S5)
			c_out <= 1'b1;
		else
			c_out <= 1'b0;

Modelsim仿真结果：检测到10010序列输出检测信号c_out比Mealy型晚一拍

附完整版Moore型代码及状态转移图：

代码功能描述：完成序列检测10010，并“可重复”使用输入

module seq_fsm(
			  input		wire		sclk,
			  input		wire		rst_n,
			  input		wire		c_in,		
			  output	reg			c_out
				);
	
	reg		[5:0]		state;
	
	parameter		[5:0]	IDLE 	=	 6'b000001;
	parameter		[5:0]	S1	 	=	 6'b000010;
	parameter		[5:0]	S2		= 	 6'b000100;
	parameter		[5:0]	S3 		= 	 6'b001000;
	parameter		[5:0]	S4		=	 6'b010000;
	parameter		[5:0]	S5		= 	 6'b100000;
	
	//状态机描述	10010
	always@(posedge sclk or negedge rst_n)
		if(rst_n == 1'b0)
			state <= IDLE;
		else
			case(state)
				IDLE:if(c_in == 1'b1)
						state <= S1;
					 else	
						state <= IDLE;
				S1:if(c_in == 1'b0)
						state <= S2;
					  else
						state <= S1;
				S2:if(c_in == 1'b0) 
						state <= S3;
					  else	
						state <= S1;
				S3:if(c_in == 1'b1)
						state <= S4;
					   else
						 state <= IDLE;
				S4:if(c_in == 1'b0)
						state <= S5;
					else
						state <= S1;
				S5:if(c_in == 1'b0)
						state <= S3;
					else
						state <= S1;
				default:state <= IDLE;
			endcase
	//状态机输出
	always@(posedge sclk or negedge rst_n)
		if(!rst_n)
			c_out <= 1'b0;
		else if(state == S5)
			c_out <= 1'b1;
		else
			c_out <= 1'b0;
endmodule

testbench代码：

`timescale 1ns/1ps
`define period_clk 20

module seq_fsm_tb;
	
	reg clk;
	reg rst_n;
	reg data;
	
	wire flag;
	wire [4:0]  data_r = 5'b10010;
	seq_fsm seq_fsm_0(
									.sclk(clk),
									.rst_n(rst_n),
									.c_in(data),	
									.c_out(flag)
									);
					
	initial clk = 1'b0;
	always#(`period_clk/2)clk = ~clk;
	
	initial begin
		rst_n = 1'b0;
		data = 1'b0;
		#202;
		rst_n = 1'b1;
		#202;
		data_send;
		#202;
		data_send_r;
		#202;
		data_send;
		#202;
		data_send_r;
		#202;
		$stop;
	end
	
	task data_send;
		integer i;
		for(i=0;i<20;i=i+1)
		begin
			@(posedge clk)
			data = i[0];
		end
	endtask
	
	task data_send_r;
		integer i;
		for(i=0;i<5;i=i+1)
		begin
			@(posedge clk)
			data = data_r[4-i];
		end
	endtask
endmodule 

状态转移图：