57--vivado 带阻滤波器

目标：
实现带阻滤波器。参数如下：
 阻带频率1：100KHz；
 阻带频率2：300KHz；
 通过频率1：50KHz；
 通过频率2：350KHz；
 通带波动：<1dB；
 阻带衰减：>40dB。

ip核coe 文件：
; XILINX CORE Generator™Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB® 9.2 and the DSP System Toolbox 9.4.
; Generated on: 07-Jun-2020 11:37:46
Radix = 16;
Coefficient_Width = 16;
CoefData = 02ec,
fee3,
ff5b,
0017,
00d5,
010b,
0066,
ff49,
fe92,
fed8,
ffc4,
0045,
ff8e,
fdfb,
fce4,
fd62,
ff2b,
00a3,
005b,
fe91,
fd41,
fe62,
01db,
0534,
05a5,
02e8,
000b,
011f,
0745,
0e98,
1045,
07b9,
f6fc,
e66a,
5f84,
e66a,
f6fc,
07b9,
1045,
0e98,
0745,
011f,
000b,
02e8,
05a5,
0534,
01db,
fe62,
fd41,
fe91,
005b,
00a3,
ff2b,
fd62,
fce4,
fdfb,
ff8e,
0045,
ffc4,
fed8,
fe92,
ff49,
0066,
010b,
00d5,
0017,
ff5b,
fee3,
02ec;

详细实现步骤可参考之前的博文。

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/06/07 11:43:39
// Design Name: 
// Module Name: bandstop
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module bandstop(
    input clk,
    input s_axis_data_tvalid,
    input s_axis_data_tvalid_1,
    output [15:0]m_axis_data_tdata_0,
     output [15:0]m_axis_data_tdata_1,
      output [15:0]m_axis_data_tdata_2,
      output [16:0]s1,//44+200
      output [16:0]s2,//200+400
      output [39:0]m_axis_data_tdata_fir,
      output [39:0]m_axis_data_tdata_fir1
    );
    
    wire event_pinc_invalid_0,event_pinc_invalid_1,event_pinc_invalid_2;
    wire event_poff_invalid_1,event_poff_invalid_0,event_poff_invalid_2;
    wire m_axis_phase_tvalid_0,m_axis_phase_tvalid_1,m_axis_phase_tvalid_2;
    wire m_axis_phase_tdata_0,m_axis_phase_tdata_1,m_axis_phase_tdata_2;
    wire m_axis_data_tvalid1,m_axis_data_tvalid2,m_axis_data_tvalid0;
    //44kHz
    dds_compiler_0 dds0 (
  .aclk(clk),                                // input wire aclk
  .m_axis_data_tvalid(m_axis_data_tvalid0),    // output wire m_axis_data_tvalid
  .m_axis_data_tdata(m_axis_data_tdata_0),      // output wire [15 : 0] m_axis_data_tdata
  .m_axis_phase_tvalid(m_axis_phase_tvalid_0),  // output wire m_axis_phase_tvalid
  .m_axis_phase_tdata(m_axis_phase_tdata_0),    // output wire [15 : 0] m_axis_phase_tdata
  .event_pinc_invalid(event_pinc_invalid_0),    // output wire event_pinc_invalid
  .event_poff_invalid(event_poff_invalid_0)    // output wire event_poff_invalid
);
    //200kHz
    dds_compiler_1 dds1 (
  .aclk(clk),                                // input wire aclk
  .m_axis_data_tvalid(m_axis_data_tvalid1),    // output wire m_axis_data_tvalid
  .m_axis_data_tdata(m_axis_data_tdata_1),      // output wire [15 : 0] m_axis_data_tdata
  .m_axis_phase_tvalid(m_axis_phase_tvalid_1),  // output wire m_axis_phase_tvalid
  .m_axis_phase_tdata(m_axis_phase_tdata_1),    // output wire [15 : 0] m_axis_phase_tdata
  .event_pinc_invalid(event_pinc_invalid_1),    // output wire event_pinc_invalid
  .event_poff_invalid(event_poff_invalid_1)    // output wire event_poff_invalid
);
    //400kHz
    dds_compiler_2 dds2(
  .aclk(clk),                                // input wire aclk
  .m_axis_data_tvalid(m_axis_data_tvalid2),    // output wire m_axis_data_tvalid
  .m_axis_data_tdata(m_axis_data_tdata_2),      // output wire [15 : 0] m_axis_data_tdata
  .m_axis_phase_tvalid(m_axis_phase_tvalid_2),  // output wire m_axis_phase_tvalid
  .m_axis_phase_tdata(m_axis_phase_tdata_2),    // output wire [15 : 0] m_axis_phase_tdata
  .event_pinc_invalid(event_pinc_invalid_0),    // output wire event_pinc_invalid
  .event_poff_invalid(event_poff_invalid_1)    // output wire event_poff_invalid
);
c_addsub_0 add1 (
  .A(m_axis_data_tdata_0),  // input wire [15 : 0] A
  .B(m_axis_data_tdata_1),  // input wire [15 : 0] B
  .S(s1)  // output wire [16 : 0] S
);
c_addsub_1 add2 (
  .A(m_axis_data_tdata_1),  // input wire [15 : 0] A
  .B(m_axis_data_tdata_2),  // input wire [15 : 0] B
  .S(s2)  // output wire [16 : 0] S
);
wire s_axis_data_tready;
wire m_axis_data_tvalid_f1;
wire m_axis_data_tvalid_f0;
fir_compiler_0 fir1 (
  .aclk(clk),                              // input wire aclk
  .s_axis_data_tvalid(s_axis_data_tvalid_1),  // input wire s_axis_data_tvalid
  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
  .s_axis_data_tdata(s1),    // input wire [23 : 0] s_axis_data_tdata
  .m_axis_data_tvalid(m_axis_data_tvalid_f0),  // output wire m_axis_data_tvalid
  .m_axis_data_tdata(m_axis_data_tdata_fir)    // output wire [39 : 0] m_axis_data_tdata
);
fir_compiler_1 fir2 (
  .aclk(clk),                              // input wire aclk
  .s_axis_data_tvalid(s_axis_data_tvalid),  // input wire s_axis_data_tvalid
  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
  .s_axis_data_tdata(s2),    // input wire [23 : 0] s_axis_data_tdata
  .m_axis_data_tvalid(m_axis_data_tvalid_f1),  // output wire m_axis_data_tvalid
  .m_axis_data_tdata(m_axis_data_tdata_fir1)    // output wire [39 : 0] m_axis_data_tdata
);


endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/06/07 13:18:49
// Design Name: 
// Module Name: tb_bandstop
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_bandstop(

    );
   reg s_axis_data_tvalid;
   reg s_axis_data_tvalid_1;
    reg clk;
  //  reg m_axis_data_tvalid;
    wire [15:0]m_axis_data_tdata_0;
    wire [15:0]m_axis_data_tdata_1;
    wire [15:0]m_axis_data_tdata_2;
    wire [16:0]s1;//44+200
    wire [16:0]s2;//200+400
    wire [39:0]m_axis_data_tdata_fir;
    wire [39:0]m_axis_data_tdata_fir1;
    bandstop u1(.clk(clk),.m_axis_data_tdata_0(m_axis_data_tdata_0),.m_axis_data_tdata_1(m_axis_data_tdata_1),
    .m_axis_data_tdata_2(m_axis_data_tdata_2),.s1(s1),.s2(s2),.s_axis_data_tvalid(s_axis_data_tvalid),.m_axis_data_tdata_fir(m_axis_data_tdata_fir),
    .m_axis_data_tdata_fir1(m_axis_data_tdata_fir1),.s_axis_data_tvalid_1(s_axis_data_tvalid_1));
    initial begin
    s_axis_data_tvalid<=1'b1;
    s_axis_data_tvalid_1<=1'b1;
    clk<=1'b0;
  
    end
    always #5 clk<=~clk;
endmodule

s1,s2为混合波，分别对其进行滤波后可发现只剩下阻带外频率的信号。