FPGA中常用写法

（1）rs232中判断数据起始位

always @(posedge clk)
begin
if(cnt_start==300)  %300是通过FPGA在线测试查看rx持续为高的大概时间确定的
process_en <= 1'b1;
else if(rx)
cnt_start <= cnt_start + 1;
else
cnt_start <= 0;
end

//
always @(posedge clk)
if(process_en)
begin
case(TS)
0:begin
if(cnt_wait==8)begin cnt_wait<=0;TS<=TS+1;end //cnt_wait持续8个时钟，防止抖动
else if(~rx)      cnt_wait<=cnt_wait+1;
else   cnt_wait<=0;
end
180:  TS <= 0;
default:TS <= TS + 1;
endcase
end
else
begin
TS       <= 0;
cnt_wait <= 0;
end

//
always @(posedge clk)
case(TS)
21: rx_buff[0] <= rx;
41: rx_buff[1] <= rx;
61: rx_buff[2] <= rx;
81: rx_buff[3] <= rx;
101:rx_buff[4] <= rx;
121:rx_buff[5] <= rx;
141:rx_buff[6] <= rx;
161:rx_buff[7] <= rx;
162:DV <= 1'b1;
163:DV <= 1'b0;

endcase

（2）查找数据头

可以将串行的数据转换乘并行，然后与固定头数据进行比较，做出正确的判断

//-------寻找信息头-------//
parameter [47:0] head_data = 48'h24_47_50_47_53_56;//$GPRMC
parameter [15:0] end_data = 16'h0D_0A;
reg [47:0] head_data_temp = 48'd0;
reg [15:0] end_data_temp = 16'd0;

always @ (posedge Clk_192K)
begin
if(data_en)
begin
head_data_temp <= {head_data_temp[39:0],dataout};
end_data_temp <= {end_data_temp[7:0],dataout};
end
end

reg flag = 0;
always @ (posedge Clk_192K)
begin
if(head_data_temp == head_data)
flag <= 1;
else if(end_data_temp == end_data)
flag <= 0;
end