数字部件设计实验二、使用Verilog语言实现3-8译码器和4-2编码器

3-8译码器

3-8译码器实现代码

• 设计文件代码：

module decoder3_8(in, out);
    input [2:0] in;
    output reg [7:0] out;
    
    always @(*)
    begin
        case(in)
        3'b000: out=8'b00000001;
        3'b001: out=8'b00000010;
        3'b010: out=8'b00000100;
        3'b011: out=8'b00001000;
        3'b100: out=8'b00010000;
        3'b101: out=8'b00100000;
        3'b110: out=8'b01000000;
        default: out=8'b10000000;
        endcase
     end

endmodule

• 约束文件代码：

# Nexys4 Pin Assignments
############################
# On-board Slide Switches  #
############################
set_property PACKAGE_PIN J15 [get_ports {in[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[0]}]
set_property PACKAGE_PIN L16 [get_ports {in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[1]}]
set_property PACKAGE_PIN M13 [get_ports {in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[2]}]

############################
# On-board led             #
############################
set_property PACKAGE_PIN H17 [get_ports out[0]]
set_property IOSTANDARD LVCMOS33 [get_ports out[0]]
set_property PACKAGE_PIN K15 [get_ports out[1]]
set_property IOSTANDARD LVCMOS33 [get_ports out[1]]
set_property PACKAGE_PIN J13 [get_ports out[2]]
set_property IOSTANDARD LVCMOS33 [get_ports out[2]]
set_property PACKAGE_PIN N14 [get_ports out[3]]
set_property IOSTANDARD LVCMOS33 [get_ports out[3]]
set_property PACKAGE_PIN R18 [get_ports out[4]]
set_property IOSTANDARD LVCMOS33 [get_ports out[4]]
set_property PACKAGE_PIN V17 [get_ports out[5]]
set_property IOSTANDARD LVCMOS33 [get_ports out[5]]
set_property PACKAGE_PIN U17 [get_ports out[6]]
set_property IOSTANDARD LVCMOS33 [get_ports out[6]]
set_property PACKAGE_PIN U16 [get_ports out[7]]
set_property IOSTANDARD LVCMOS33 [get_ports out[7]]

4-2编码器

实现代码

• 设计文件：

module encoder4_2(in, out

    );
    input [4:0] in;
    output reg [1:0] out;

    
    always @(*)
   
    begin
        if(in[3]) out = 2'b11;
        else if(in[2]) out = 2'b10;
        else if(in[1]) out = 2'b01;
        else           out = 2'b00;
        
        //implementation2
//        case(in)
//        4'b1000: out = 2'b00;
//        4'bx100: out = 2'b00;
//        4'bxx10: out = 2'b00;
//        4'bxxx1: out = 2'b00;
//        default:;
//        endcase
    end
            
endmodule

• 约束文件：

# Nexys4 Pin Assignments
############################
# On-board Slide Switches  #
############################
set_property PACKAGE_PIN J15 [get_ports {in[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[0]}]
set_property PACKAGE_PIN L16 [get_ports {in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[1]}]
set_property PACKAGE_PIN M13 [get_ports {in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[2]}]
set_property PACKAGE_PIN R15 [get_ports {in[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {in[3]}]
############################
# On-board led             #
############################
set_property PACKAGE_PIN H17 [get_ports out[0]]
set_property IOSTANDARD LVCMOS33 [get_ports out[0]]
set_property PACKAGE_PIN K15 [get_ports out[1]]
set_property IOSTANDARD LVCMOS33 [get_ports out[1]]

最后

最近忙期中，更新速度慢了些，不过期中期末无缝连接，可能接下来两个月都会更得没那么频繁了，暂时定为三周一次吧，反正也不靠这个恰饭嘛，不过毕竟也是自己的一个兴趣，也不想就这么放弃掉。