Quartus推荐的时序优化方式

• When adding register stages to pipeline control signals, turn off the Auto Shift Register Replacement option (Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis)) for these registers. By default, chains of registers can be converted to a RAM-based implementation based on performance and resource estimates. Since pipelining helps meet timing requirements over long distance, this assignment ensures that control signals are not converted.（通过更改设置防止流水化的控制信号被转换为ram）

• In general, after allocating the clocks in a design, use global networks for the highest fan-out control signals. When a global network signal distributes a high fan-out control signal, the global signal can drive
  logic anywhere in the device. Similarly, when using a regional network signal, the driven must be in one quadrant of the device, or half the device for a dual-regional network signal. （使用全局时钟网络的信号可以驱动器件内部的任何地方的资源，若不是，则最好将该信号驱动的资源放置在整个器件的1/4区域或者1/2区域内）

• Physical synthesis for combinational logic—When the Perform physical synthesis for combinational logic is turned on, the report panel identifies logic that physical synthesis can modify. You can use this information to modify the design so that the associated optimization can be turned off to save compile time.（通过对EDA软件设置，使其可以自动优化组合逻辑以满足时序）

• Register duplication—This technique is most useful where registers have high fan-out, or where the fan-out is in physically distant areas of the device. Review the netlist optimizations report and consider manually duplicating registers automatically added by physical synthesis. You can also locate the original and duplicate registers in the Chip Planner. Compare their locations, and if the fan-out is improved, modify the code and turn off register duplication to save compile time.（对于多扇出的寄存器，可以采用寄存器复制的方式来优化时序）

• Register retiming—This technique is particularly useful where some combinatorial paths between registers exceed the timing goal while other paths fall short. If a design is already heavily pipelined, register retiming is less likely to provide significant performance gains since there should not be significantly unbalanced levels of logic across pipeline stages。（寄存器配平，用于一条路径中一部分组合逻辑超长，另一部分很短的情况。将组合逻辑均分在各个级别的流水线进行时序优化）。

• 时序命令约束

  • Apply multicycle constraints in your design wherever single-cycle timing analysis is not required.
  • Apply False Path constraints to all asynchronous clock domain crossings or resets in the design. This technique prevents overconstraining and the Fitter focuses only on critical paths to reduce compile time. （false path 约束用于所有的异步时钟域传输以及异步复位）。However, over constraining timing critical clock domains can sometimes provide better timing results and lower compile times than physical synthesis.
  • Overconstrain rather than using physical synthesis when the slack improvement from physical synthesis is near zero. Overconstrain the frequency requirement on timing critical clock domains by using setup uncertainty.
  • When evaluating the effect of constraint changes on performance and runtime, compile the design with at least three different seeds to determine the average performance and runtime effects. Different constraint combinations produce various results. Three samples or more establishes a performance trend. Modify your constraints based on performance improvement or decline.（条件允许的情况下，通过多次更改编译种子来分析时序约束方向或者时序优化方向）
  • Leave settings at the default value whenever possible. Increasing performance constraints can increase the compile time significantly. While those increases may be necessary to close timing on a design, using the default settings whenever possible minimizes compile time.（尽量使用默认设置，增加性能的设置往往会延长编译时间）。

• To close timing in high speed designs, review paths with the largest timing failures. Correcting a single, large timing failure can result in a very significant timing improvement.Review the register placement and routing paths by clicking Tools > Chip Planner. Large timing failures on high fan-out control signals can be caused by any of the following conditions:（优化一个时序违例的关键路径可能会导致整体时序的提升）时序优化三板斧：
  • Sub-optimal use of global networks（走全局时钟网络）
  • Signals that traverse the chip on local routing without pipelining（流水化）
  • Failure to correct high fan-out by register duplication（寄存器复制）

• For high-speed and high-bandwidth designs, optimize speed by reducing bus width and wire usage. To reduce wire use, move the data as little as possible. For example, if a block of logic functions on a few bits of a word, store inactive bits in a fifo or memory. Memory is cheaper and denser than registers and reduces wire usage.（对于高速多位宽的数据流处理，可以将暂时不参加运算的那部分数据存入fifo or memory以减少运算位宽。fifo or memory比LUT缓冲数据来的更加密集和经济，减少资源占用，有利于优化时序。比如重心算法将TDC和总能量、evt_num做fifo缓冲就是例证）。