计算机组成原理｜实现R型指令的CPU设计实验
实现R型指令的CPU设计实验
一、实验目的与要求
-
实验目的：
（1）掌握MISP R型指令的数据通路设计，掌握指令流和数据流的控制方法
（2）掌握完整的单周期CPU顶层模块的设计方法
（3）实现MISP R型指令的功能 -
实验要求：
（1）在实验三~六的基础上，编写一个CPU模块，实现实验八指定的R型指令
（2）编写一个实验验证的顶层模块 -
模块设计说明
模块sy8_top为顶层模块，负责连接其他部分模块，同时对Rom_out 与OP进行转换。
模块PC则是实现PC自增的操作
模块ALU实现运算功能
模块jcq实现寄存器堆功能
模块LED-0实现了对输出的选择
二、实验设计与程序代码
module sy8_top(rst,clk,F_LED_SW,LED);
input rst;
input clk;
input F_LED_SW;
output [31:0] LED;
wire [31:0] Rom_out;
wire [31:0] A,B;
reg [3:0] OP;
wire ZF,OF;
wire [31:0] F;
reg Write_Reg;
PC Pp(
.rst(rst),
.clk(clk),
.Rom_out(Rom_out)
);
//OP<=Rom_out[31:26];
// rs<=Rom_out[25:21];
// rt<=Rom_out[20:16];
// rd<=Rom_out[15:11];
//func<=Rom_out[5:0];
always@(*)
begin
OP=4'b0000;
Write_Reg=1'b0;
if(OP==6'b00_0000)
begin Write_Reg=1'b1;
case(Rom_out[5:0])
6'b10_0000:OP=4'b0100;
6'b10_0010:OP=4'b0101;
6'b10_0100:OP=4'b0000;
6'b10_0101:OP=4'b0001;
6'b10_0110:OP=4'b0010;
6'b10_0111:OP=4'b0011;
6'b10_1011:OP=4'b0110;
6'b00_0100:OP=4'b0111;
default;
endcase
end
end
jcq j1(
.R_Addr_A(Rom_out[25:21]),
.R_Addr_B(Rom_out[20:16]),
.W_Addr(Rom_out[15:11]),
.Write_Reg(Write_Reg),
.W_Data(F),
.R_Data_A(A),
.R_Data_B(B),
.clk(~clk),
.rst(rst));
ALU A1(
.A(A),
.B(B),
.OP(OP),
.F(F),
.ZF(ZF),
.OF(OF));
LED_0 l0(
.F_LED_SW(F_LED_SW),
.ZF(ZF),
.OF(OF),
.F(F),
.LED(LED));
Endmodule
PC：
module PC(rst,clk,Rom_out);
input rst;
input clk;
output [31:0] Rom_out;
reg [31:0] PC;
wire [31:0] PC_t;
assign PC_t=PC+32'h4;
always@(posedge rst or negedge clk)
begin
if(rst) PC<=32'h0000_0000;
else PC<=PC_t;
end
Inst_Rom Ir1(
.clka(clk),
.addra(PC[7:2]),
.douta(Rom_out));
Endmodule
jcq：
module jcq(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,R_Data_A,R_Data_B,clk,rst);
input [4:0] R_Addr_A;
input [4:0] R_Addr_B;
input [4:0] W_Addr;
input Write_Reg;
input [31:0] W_Data;
input clk;
input rst;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0]REG_Files[31:0];
reg [5:0] i;
initial
begin
for(i=0;i<32;i=i+1)
REG_Files[i]<=32'b0+i;
end
always@(posedge clk or posedge rst)
begin
if(rst)
for(i=0;i<32;i=i+1)
REG_Files[i]<=32'b0+i;
else
begin
if(Write_Reg&&W_Addr!=0)
REG_Files[W_Addr]<=W_Data;
end
end
assign R_Data_A=REG_Files[R_Addr_A]; //读操作
assign R_Data_B=REG_Files[R_Addr_B];
endmodule
ALU&LED_0：
module ALU(A,B,OP,F,ZF,OF);
input [31:0]A,B;
input [3:0]OP;
output reg [31:0]F;
output reg OF,ZF;
reg [32:0] CF;
always@(*)
begin
case(OP)
3'b0000:CF=A&B;
3'b0001:CF=A|B;
3'b0010:CF=A^B;
3'b0011:CF=~(A|B);
3'b0100:CF=A+B;
3'b0101:CF=A-B;
3'b0110:CF=A<B;
3'b0111:CF=B<<A;
default;
endcase
F=CF[31:0];
OF=A[31]^B[31]^F[31]^CF[32];
ZF= F[31:0]==0;
end
endmodule
module LED_0(F_LED_SW,ZF,OF,F,LED);
input F_LED_SW,ZF,OF;
input wire[31:0] F;
output reg [31:0] LED;
always @(*)
begin
case(F_LED_SW)
1'b0: LED=F[31:0];
1'b1: begin LED[0]=ZF;LED[1]=OF;LED[31:2]=30'b0;end
endcase
end
endmodule
三、实验仿真
仿真代码
module test;
// Inputs
reg rst;
reg clk;
// Outputs
wire [31:0] led;
wire ZF;
wire OF;
// Instantiate the Unit Under Test (UUT)
sy8 uut (
.rst(rst),
.clk(clk),
.led(led),
.ZF(ZF),
.OF(OF)
);
initial begin
// Initialize Inputs
clk = 0;
rst=1'b1; #25 rst=1'b0;
// Wait 100 ns for global reset to finish
// Add stimulus here
begin
#5 forever #5 clk=~clk;
end
end
endmodule
仿真波形
四、电路图
五、引脚配置（约束文件）
NET “F[31]” IOSTANDARD = LVCMOS18;
NET “F[30]” IOSTANDARD = LVCMOS18;
NET “F[29]” IOSTANDARD = LVCMOS18;
NET “F[28]” IOSTANDARD = LVCMOS18;
NET “F[27]” IOSTANDARD = LVCMOS18;
NET “F[26]” IOSTANDARD = LVCMOS18;
NET “F[25]” IOSTANDARD = LVCMOS18;
NET “F[24]” IOSTANDARD = LVCMOS18;
NET “F[23]” IOSTANDARD = LVCMOS18;
NET “F[22]” IOSTANDARD = LVCMOS18;
NET “F[21]” IOSTANDARD = LVCMOS18;
NET “F[20]” IOSTANDARD = LVCMOS18;
NET “F[19]” IOSTANDARD = LVCMOS18;
NET “F[18]” IOSTANDARD = LVCMOS18;
NET “F[17]” IOSTANDARD = LVCMOS18;
NET “F[16]” IOSTANDARD = LVCMOS18;
NET “F[15]” IOSTANDARD = LVCMOS18;
NET “F[14]” IOSTANDARD = LVCMOS18;
NET “F[13]” IOSTANDARD = LVCMOS18;
NET “F[12]” IOSTANDARD = LVCMOS18;
NET “F[11]” IOSTANDARD = LVCMOS18;
NET “F[10]” IOSTANDARD = LVCMOS18;
NET “F[9]” IOSTANDARD = LVCMOS18;
NET “F[8]” IOSTANDARD = LVCMOS18;
NET “F[7]” IOSTANDARD = LVCMOS18;
NET “F[6]” IOSTANDARD = LVCMOS18;
NET “F[5]” IOSTANDARD = LVCMOS18;
NET “F[4]” IOSTANDARD = LVCMOS18;
NET “F[3]” IOSTANDARD = LVCMOS18;
NET “F[2]” IOSTANDARD = LVCMOS18;
NET “F[1]” IOSTANDARD = LVCMOS18;
NET “F[0]” IOSTANDARD = LVCMOS18;
NET “clk” IOSTANDARD = LVCMOS18;
NET “rst” IOSTANDARD = LVCMOS18;
NET “sw” IOSTANDARD = LVCMOS18;
NET “clk” PULLDOWN;
NET “rst” PULLDOWN;
NET “sw” PULLDOWN;
PlanAhead Generated physical constraints
NET “F[31]” LOC = R1;
NET “F[30]” LOC = P2;
NET “F[29]” LOC = P1;
NET “F[28]” LOC = N2;
NET “F[27]” LOC = M1;
NET “F[26]” LOC = M2;
NET “F[25]” LOC = L1;
NET “F[24]” LOC = J2;
NET “F[23]” LOC = G1;
NET “F[22]” LOC = E1;
NET “F[21]” LOC = D2;
NET “F[20]” LOC = A1;
NET “F[19]” LOC = L3;
NET “F[18]” LOC = G3;
NET “F[17]” LOC = K4;
NET “F[16]” LOC = G4;
NET “F[15]” LOC = K1;
NET “F[14]” LOC = J1;
NET “F[13]” LOC = H2;
NET “F[12]” LOC = G2;
NET “F[11]” LOC = F1;
NET “F[10]” LOC = E2;
NET “F[9]” LOC = D1;
NET “F[8]” LOC = B1;
NET “F[7]” LOC = B2;
NET “F[6]” LOC = N3;
NET “F[5]” LOC = M3;
NET “F[4]” LOC = K3;
NET “F[3]” LOC = H3;
NET “F[2]” LOC = N4;
NET “F[1]” LOC = L4;
NET “F[0]” LOC = J4;
NET “clk” LOC = AA4;
NET “rst” LOC = R4;
NET “sw” LOC = AB6;
NET “clk” CLOCK_DEDICATED_ROUTE = FALSE;
六、思考与探索
实验结果记录：
序号 指令 执行结果 ZF OF 结论
0 00000827 FFFFFFFF 0 0 结果正确
1 0001102b 00000001 0 0 结果正确
2 00421820 00000002 0 0 结果正确
3 00622020 00000003 0 0 结果正确
4 00832820 00000005 0 0 结果正确
5 00a33020 00000007 0 0 结果正确
6 00463804 0000000E 0 0 结果正确
7 00a64820 0000000C 0 0 结果正确
8 01264004 00007000 0 0 结果正确
9 00284826 FFFF8FFF 0 0 结果正确
10 01215020 FFFF8FFE 0 0 结果正确
11 01075822 00006FF2 0 0 结果正确
12 00e86022 FFFF900E 0 0 结果正确
13 012c6824 FFFF800E 0 0 结果正确
14 012c7025 FFFF9FFF 0 0 结果正确
15 00c77825 0000000F 0 0 结果正确
16 00c78027 FFFFFFF0 0 0 结果正确
17 00e38820 00000010 0 0 结果正确
18 02289004 70000000 0 0 结果正确
19 02239804 00020000 0 0 结果正确
20 00f3a004 80000000 0 0 结果正确
21 0281a820 7FFFFFFF 0 1 结果正确
22 0255b025 7FFFFFFF 0 1 结果正确
23 0296b820 FFFFFFFF 0 1 结果正确
24 0296c022 00000001 0 0 结果正确
25 02d4c822 FFFFFFFF 0 1 结果正确
26 0241d026 8FFFFFFF 0 1 结果正确
27 02d4d82b 00000001 0 1 结果正确
28 0354e02b 00000000 1 1 结果正确
29 02c2e820 80000000 0 1 结果正确
30 0282f022 7FFFFFFF 0 1 结果正确
31 017af820 90006FF1 0 1 结果正确