HDLBits Verilog编程题139 Mealy状态机时序检测设计

139.Exams/ece241 2013 q8（Q8:Design a Mealy FSM）
原题：Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
简单说明：设计Mealy状态机，检测‘101’时序；输入信号:x；输出信号:z
链接：https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q8
Mealy状态转换图：

注意：Mealy状态机的输出是现态和输入的函数
aresetn：异步复位，低电平有效

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    reg [2:0] state_c, state_n;
    parameter S0=0, S1=1, S2=2, S3=3;
    wire S02S1, S12S2, S22S3, S32S1;
    always@(posedge clk or negedge aresetn) begin
        if(!aresetn)
            state_c <= S0;
        else
            state_c <= state_n;
    end
    
    always@(*) begin
        case(state_c)
            S0:begin
                if(S02S1)
                    state_n = S1;
                else
                    state_n = S0;
            end
            S1:begin
                if(S12S2)
                    state_n = S2;
                else
                    state_n = state_c;
            end
            S2:begin
                if(S22S3)
                    state_n = S3;
                else
                    state_n = S0;
            end
            S3:begin
                if(S32S1)
                    state_n = S1;
                else 
                    state_n = S2;
            end
        endcase
    end
    assign S02S1 = state_c==S0 && x==1;
    assign S12S2 = state_c==S1 && x==0;
    assign S22S3 = state_c==S2 && x==1;
    assign S32S1 = state_c==S3 && x==1;
    
    assign z = state_c==S2 && x==1;
        
endmodule