HDLBits记录（二）
记录在HDLBits上做的题目,如有错误，欢迎指正。
目录
- 3 Circuits
- 3.1 Combinational Logic
- 3.1.1 Basic Gates
- 3.1.2 Multiplexers
- 3.1.3 Arithmetic Circuits
- 3.1.4 Karnaugh Map to Circuit
3 Circuits
3.1 Combinational Logic
3.1.1 Basic Gates
1 wire
module top_module (
input in,
output out);
assign out = in;
endmodule
2 GND
module top_module (
output out);
assign out = 1'b0;
endmodule
3 NOR
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
4 another gate
module top_module (
input in1,
input in2,
output out);
assign out = in1 & (~in2);
endmodule
5 two gate
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = (in1 ^~ in2) ^ in3;
endmodule
6 more logic gates
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb );
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = a ^~ b;
assign out_anotb = a & (~b);
endmodule
7 7420 chip
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
8 truth table
module top_module(
input x3,
input x2,
input x1,
output f );
assign f = ((~x3) & x2 & (~x1)) | ((~x3) & x2 & x1) | (x3 & (~x2) & x1) | (x3 & x2 & x1);
endmodule
9 two-bits equality
module top_module ( input [1:0] A, input [1:0] B, output z );
assign z = (A == B) ? 1 : 0;
endmodule
10 sample circuits A
module top_module (input x, input y, output z);
assign z= (x ^ y) & x;
endmodule
11 sample circuits B
module top_module ( input x, input y, output z );
assign z = x ^~ y;
endmodule
12 combine circuits A and B
module top_module (input x, input y, output z);
wire z1,z2;
assign z1= (x ^ y) & x;
assign z2 = x ^~ y;
assign z = (z1 | z2) ^ (z1 & z2);
endmodule
13 ring or vibrate
module top_module (
input ring,
input vibrate_mode,
output ringer,
output motor );
assign {ringer, motor} = ring ? (vibrate_mode ? 2'b01 : 2'b10) : 2'b00;
endmodule
14 thermostat
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan );
assign heater = mode ? (too_cold ? 1'b1 : 1'b0) : 1'b0;
assign aircon = ~mode ? (too_hot ? 1'b1 : 1'b0) : 1'b0;
assign fan = heater | aircon | fan_on;
endmodule
15 3-bit population count
module top_module(
input [2:0] in,
output [1:0] out );
reg [1:0] i;
always @(*) begin
out = 2'd0;
for(i = 0; i < 3; i = i + 1'b1)
if (in[i] == 1)
out = out + 1'b1;
else
out = out;
end
endmodule
16 gates and vectors
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign {out_both[2], out_both[1], out_both[0]} = {in[3] & in[2], in[2] & in[1], in[1] & in[0]};
assign {out_any[3], out_any[2], out_any[1]} = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign {out_different[3], out_different[2], out_different[1], out_different[0]} = {in[0] ^ in[3], in[3] ^ in[2], in[2] ^ in[1], in[1] ^ in[0]};
endmodule
16 gates longer vectors
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_both = in[99:1] & in[98:0];
assign out_any = in[99:1] | in[98:0];
assign out_different = in[99:0] ^ {in[0], in[99:1]};
endmodule
3.1.2 Multiplexers
1 2 to 1 multiplexers
module top_module(
input a, b, sel,
output out );
assign out = sel ? b : a;
endmodule
2 2 to 1 bus multiplexers
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = sel ? b : a;
endmodule
3 9 to 1 multiplexers
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default: out = 16'hffff;
endcase
end
endmodule
4 256 to 1 multiplexers
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
5 256 to 1 4-bit multiplexers
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4]};
endmodule
3.1.3 Arithmetic Circuits
1 half adder
module top_module(
input a, b,
output cout, sum );
assign {cout,sum} = a + b;
endmodule
2 full adder
module top_module(
input a, b, cin,
output cout, sum );
assign {cout,sum} = a + b + cin;
endmodule
2 3-bit binary adder
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
adder adder_1(.a(a[0]), .b(b[0]), .cin(cin), .cout(cout[0]), .sum(sum[0]));
adder adder_2(.a(a[1]), .b(b[1]), .cin(cout[0]), .cout(cout[1]), .sum(sum[1]));
adder adder_3(.a(a[2]), .b(b[2]), .cin(cout[1]), .cout(cout[2]), .sum(sum[2]));
endmodule
//全加器
module adder(
input a, b, cin,
output cout, sum );
assign {cout,sum} = a + b + cin;
endmodule
4 adder
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
wire cout_1,cout_2,cout_3;
assign sum = x + y;
endmodule
5 sined addition overflow
6 100-bit binary adder
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout, sum} = a + b + cin;
endmodule
7 4- digit BCD adder
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [2:0] cout_temp;
bcd_fadd bcd_fadd_0(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_temp[0]), .sum(sum[3:0]));
bcd_fadd bcd_fadd_1(.a(a[7:4]), .b(b[7:4]), .cin(cout_temp[0]), .cout(cout_temp[1]), .sum(sum[7:4]));
bcd_fadd bcd_fadd_2(.a(a[11:8]), .b(b[11:8]), .cin(cout_temp[1]), .cout(cout_temp[2]), .sum(sum[11:8]));
bcd_fadd bcd_fadd_3(.a(a[15:12]), .b(b[15:12]), .cin(cout_temp[2]), .cout(cout), .sum(sum[15:12]));
endmodule
3.1.4 Karnaugh Map to Circuit
1 3-variable
module top_module(
input a,
input b,
input c,
output out );
assign out = a | ((~a) & c) | (b & (~c));
endmodule
2 4-variable 1
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ((~b) & (~c)) | ((~a) & (~d)) | (b&c&d) | (a&c&d);
endmodule
3 4-variable 2
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a | ((~a) & (~b) & (c));
endmodule
4 4-variable 3
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~a&~b&~c&d | ~a&~b&c&~d | ~a&b&~c&~d | ~a&b&c&d | a&b&~c&d | a&b&c&~d | a&~b&~c&~d | a&~b&c&d;
endmodule
5 minimum SOP and POS