FPGA的中值滤波器实现
缺陷版本
！有缺陷，待改进
中值滤波是图像处理中的基础算法，用于平滑图像，特别是消除椒盐噪声，对于点状噪声和干扰脉冲有比较好的效果。
传统的中值滤波算法是将灰度图像中的一点以其邻域的中值填充，因此实际应用中值滤波的时候只需要确定邻域形状、大小。
中值确定的经典算法是先通过将所有邻域像素排序，再取其中值。如果使用冒泡排序的话，就需要 n(n−1)2 次像素比较，时间复杂度为 O(n2) 。为此改进的中值滤波是将二维所有像素全部排序分解为多个一维排序。示例如下，选择3*3的模板，将其分解为3个一维的像素先比较，选出中值，再将3个得出的中值进行比较得出最终的中值。
Verilog 实现
middle_comparator.v
module middle_comparator
(input clk,
input rst,
input [7:0] pixel_1,
input [7:0] pixel_2,
input [7:0] pixel_3,
output reg [7:0] pixel_middle
);
/*
wire [7:0] max;
wire [7:0] max_;
*/
always @(posedge clk or negedge rst)
begin
if(!rst)
pixel_middle <= 0;
else
begin
if(pixel_1 >= pixel_2)
begin
if(pixel_2 >= pixel_3)
pixel_middle <= pixel_2;
else if(pixel_2 < pixel_3)
begin
if(pixel_1 >= pixel_3)
pixel_middle <= pixel_3;
else if(pixel_1 < pixel_3)
pixel_middle <= pixel_1;
end
end
else if(pixel_1 < pixel_2)
begin
if(pixel_1 >= pixel_3)
pixel_middle <= pixel_1;
else if(pixel_1 < pixel_3)
begin
if(pixel_2 >= pixel_3)
pixel_middle <= pixel_3;
else if(pixel_2 < pixel_3)
pixel_middle <= pixel_2;
end
end
end
endmiddle_filter.v
module middle_filter
(input clk,
input rst,
input [7:0] pixel_1_1,
input [7:0] pixel_1_2,
input [7:0] pixel_1_3,
//pixel of the first row
input [7:0] pixel_2_1,
input [7:0] pixel_2_2,
input [7:0] pixel_2_3,
//pixel of the second row
input [7:0] pixel_3_1,
input [7:0] pixel_3_2,
input [7:0] pixel_3_3,
//pixel of the third row
output [7:0] pixel_middle
);
wire [7:0] pixel_middle_1;
wire [7:0] pixel_middle_2;
wire [7:0] pixel_middle_3;
middle_comparator middle_U1(
.clk(clk),
.rst(rst),
.pixel_1(pixel_1_1),
.pixel_2(pixel_1_2),
.pixel_3(pixel_1_3),
.pixel_middle(pixel_middle_1)
);
middle_comparator middle_U2(
.clk(clk),
.rst(rst),
.pixel_1(pixel_2_1),
.pixel_2(pixel_2_2),
.pixel_3(pixel_2_3),
.pixel_middle(pixel_middle_2)
);
middle_comparator middle_U3(
.clk(clk),
.rst(rst),
.pixel_1(pixel_3_1),
.pixel_2(pixel_3_2),
.pixel_3(pixel_3_3),
.pixel_middle(pixel_middle_3)
);
middle_comparator middle_U4(
.clk(clk),
.rst(rst),
.pixel_1(pixel_middle_1),
.pixel_2(pixel_middle_2),
.pixel_3(pixel_middle_3),
.pixel_middle(pixel_middle)
);
endmoduleRtl Viewer
使用资源
改进版本
分别对每一行进行排序得到每一行的最大值、最小值和中间值，再分别将每一行的最大值、最小值和中间值归为一组再进行排序，取最大值组的最小值，中间值组的中间值以及最小值组的最小值。即：
min=Min(Max1，Max2，Max3)mid=Mid(Mid1，Mid2，Mid3)max=Max(Min1，Min2，Min3)
对 min、mid和max 进行比较，其 final_mid=Mid(min，mid，max) 。
Verilog实现
middle_comparator.v
module middle_comparator
(input clk,
input rst,
input [7:0] pixel_1,
input [7:0] pixel_2,
input [7:0] pixel_3,
output reg [7:0] pixel_middle,
output reg [7:0] pixel_max,
output reg [7:0] pixel_min
);
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
pixel_middle <= 0;
pixel_max <= 0;
pixel_min <= 0;
end
else
begin
if(pixel_1 >= pixel_2)
begin
if(pixel_1 < pixel_3)
begin
pixel_max <= pixel_3;
pixel_middle <= pixel_1;
pixel_min <= pixel_2;
end
else
begin
if(pixel_2 >= pixel_3)
begin
pixel_max <= pixel_1;
pixel_middle <= pixel_2;
pixel_min <= pixel_3;
end
else
begin
pixel_max <= pixel_1;
pixel_middle <= pixel_3;
pixel_min <= pixel_2;
end
end
end
else
begin
if(pixel_1 >= pixel_3)
begin
pixel_max <= pixel_2;
pixel_middle <= pixel_1;
pixel_min <= pixel_3;
end
else
begin
if(pixel_2 >= pixel_3)
begin
pixel_max <= pixel_2;
pixel_middle <= pixel_3;
pixel_min <= pixel_1;
end
else
begin
pixel_max <= pixel_3;
pixel_middle <= pixel_2;
pixel_min <= pixel_1;
end
end
end
end
end
endmodulemiddle_filter.v
module middle_filter
(input clk,
input rst,
input [7:0] pixel_1_1,
input [7:0] pixel_1_2,
input [7:0] pixel_1_3,
//pixel of the first row
input [7:0] pixel_2_1,
input [7:0] pixel_2_2,
input [7:0] pixel_2_3,
//pixel of the second row
input [7:0] pixel_3_1,
input [7:0] pixel_3_2,
input [7:0] pixel_3_3,
//pixel of the third row
output [7:0] pixel_middle
);
wire [7:0] L1_Max;
wire [7:0] L1_Min;
wire [7:0] L1_Mid;
wire [7:0] L2_Max;
wire [7:0] L2_Min;
wire [7:0] L2_Mid;
wire [7:0] L3_Max;
wire [7:0] L3_Min;
wire [7:0] L3_Mid;
wire [7:0] Max_Min;
wire [7:0] Mid_Mid;
wire [7:0] Min_Max;
middle_comparator middle_L1(
.clk(clk),
.rst(rst),
.pixel_1(pixel_1_1),
.pixel_2(pixel_1_2),
.pixel_3(pixel_1_3),
.pixel_middle(L1_Mid),
.pixel_max(L1_Max),
.pixel_min(L1_Min)
);
middle_comparator middle_L2(
.clk(clk),
.rst(rst),
.pixel_1(pixel_2_1),
.pixel_2(pixel_2_2),
.pixel_3(pixel_2_3),
.pixel_middle(L2_Mid),
.pixel_max(L2_Max),
.pixel_min(L2_Min)
);
middle_comparator middle_L3(
.clk(clk),
.rst(rst),
.pixel_1(pixel_3_1),
.pixel_2(pixel_3_2),
.pixel_3(pixel_3_3),
.pixel_middle(L3_Mid),
.pixel_max(L3_Max),
.pixel_min(L3_Min)
);
middle_comparator middle_Max(
.clk(clk),
.rst(rst),
.pixel_1(L1_Max),
.pixel_2(L2_Max),
.pixel_3(L3_Max),
.pixel_min(Min_Max)
);
middle_comparator middle_Mid(
.clk(clk),
.rst(rst),
.pixel_1(L1_Mid),
.pixel_2(L2_Mid),
.pixel_3(L3_Mid),
.pixel_middle(Mid_Mid)
);
middle_comparator middle_Min(
.clk(clk),
.rst(rst),
.pixel_1(L1_Min),
.pixel_2(L2_Min),
.pixel_3(L3_Min),
.pixel_max(Max_Min)
);
middle_comparator middle_U7(
.clk(clk),
.rst(rst),
.pixel_1(Max_Min),
.pixel_2(Mid_Mid),
.pixel_3(Min_Max),
.pixel_middle(pixel_middle)
);
endmoduleRTL Viewer
使用资源
仿真结果
本作品采用知识共享署名-非商业性使用-相同方式共享 3.0 中国大陆许可协议进行许可。