由于后续的工作需要,大概率会进行一些验证的工作,因此我非常机智的先把gen_uvm_agent脚本写好。gen_uvm_agent只用来生成简单的握手型接口的全套代码,同时也会生成一个自测环境用于行为确认。
1.键入agent的名字,比如vbn:
[xiaotu@xiaotu-eda ~/Git_Path/gen_uvm_agent/gen_uvm_agent]$./gen_uvm_agent vbn
2.如果当前目录有vbn.cfg,则直接读取,否则跳出来一个配置文件,配置一下;可配置选项只有三个:
SIGNAL WIDTH RANDOM(Y/N)
data 32 Y
crc 8 N
last 1 Y
SIGNAL:接口的信号名,默认所有的transaction的信号都会被打到接口上;
WIDTH:信号位宽,只支持数字;
RANDOM:是否为rand信号;
3.报错cfg文件,之后键入y:
/home/xiaotu/Git_Path/gen_uvm_agent/gen_uvm_agent/./gen_uvm_agent is working
Please input y after complete: y
4.进入vbn_utils/test/目录,make cmp,检查有无编译问题:
if [ -x .././sim_base/exec/simv ]; then chmod -x .././sim_base/exec/simv; fi
g++ -o .././sim_base/exec/simv -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir -rdynamic uvm_dpi.o uvm_verdi_dpi.o amcQwB.o _prev_archive_1.so _csrc0.so SIM_l.o _csrc0.so rmapats_mop.o rmapats.o rmar.o rmar_llvm_0_1.o rmar_llvm_0_0.o /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libzerosoft_rt_stubs.so /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libvirsim.so /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/liberrorinf.so /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libsnpsmalloc.so /tools/synopsys/verdi/Verdi3_L-2016.06-1/share/PLI/VCS/LINUXAMD64/pli.a /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libvcsnew.so /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libsimprofile.so /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libuclinative.so -Wl,-whole-archive /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/libvcsucli.so -Wl,-no-whole-archive ./../sim_base/exec/simv.daidir/vc_hdrs.o _vcs_pli_stub_.o /tools/synopsys/vcs/vcs-mx_vL-2016.06/linux64/lib/vcs_save_restore_new.o /tools/synopsys/verdi/Verdi3_L-2016.06-1/share/PLI/VCS/LINUX64/pli.a -ldl -lm -lc -lpthread -ldl
.././sim_base/exec/simv up to date
make[1]: Leaving directory `/home/xiaotu/Git_Path/gen_uvm_agent/gen_uvm_agent/vbn_utils/test/csrc'
CPU time: 4.580 seconds to compile + .153 seconds to elab + .220 seconds to link
Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
[xiaotu@xiaotu-eda ~/Git_Path/gen_uvm_agent/gen_uvm_agent/vbn_utils/test]$
5.make run seed=0,之后verdi -ssf sim_base/wave/sanity_case_0.fsdb &打开波形,检查博兴行为是否符合预期:
.
├── src
│ ├── vbn_agent.sv
│ ├── vbn_driver.sv
│ ├── vbn_interface.sv
│ ├── vbn_monitor.sv
│ ├── vbn_ready_drv.sv
│ ├── vbn_scb.sv
│ ├── vbn_sequencer.sv
│ ├── vbn_sequence.sv
│ └── vbn_transaction.sv
├── test
│ ├── base_test.sv
│ ├── check_fail.pl
│ ├── harness.sv
│ ├── Makefile
│ ├── run.do
│ ├── sanity_case.sv
│ ├── tr_db.log
│ ├── vbn_env.sv
│ └── vbn_sim.lst
└── vbn_utils.lst
为了能过完成自测,driver中需要单独增加一个port用于讲transaction直接输出:
`uvm_info("vbn_driver", "drive a pkt start", UVM_HIGH);
`ifdef UTILS_TEST
ap.write(req.clone()));
`endif
this.drive_pkt(req);
seq_item_port.item_done();
通过UTILS_TEST宏来隔开这个port,因为平常时候时候是不需要这个通道的。
链接:https://pan.baidu.com/s/1RBj0Qoh7HRrR4MMrKngDoQ
提取码:kmtd
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