8个彩灯闪烁的代码Verilog HDL

module light8(clk100khz,light);
input clk100khz;
 output[7:0] light;
  parameter len=7;

  reg[7:0] light;
  reg[25:0] count,count1;
  reg clk,clk1,clk2,b;
  reg[1:0] flag;//flag shi zhuangtai
reg [5:0] j;
  initial b=1'b1;
initial j=0;
initial flag=0;
  always@(posedge clk100khz)
    begin
      if(count=='d49999)
        begin clk1=~clk1; count<=0; end
      else
        begin count<=count+1'b1; end
    end

  always@(posedge clk100khz)
    begin
      if(count1=='d4999)
        begin clk2=~clk2; count1<=0; end
      else
        begin count1<=count1+1'b1; end
    end
  
  always@(posedge clk100khz)
    begin
      if(b)
        clk<=clk1;
      else
        clk<=clk2;
    end
 
always@ (posedge clk)
begin
if(flag==0)
begin
if(j==0)
begin
light<=8'b11111111;j<=j+1;
end
else if(j==3'b01)
begin
light<=8'b00000000;j<=j+1;
end
if(light[0]==0)
flag<=2'b01;
end

else if(flag==2'b01)
begin
if(j==2)
begin
light<=8'b10000000;
j<=j+1;
end
else
begin
light<={light[0],light[len:1]};
j<=j+1;
if(light[1]==1)
flag<=2'b10;


end
end


else if(flag==2'b10)
begin
if(j>0)
begin 
light<=8'b10101010;j<=0;
end
else
begin
light<={light[0],light[len:1]};
flag<=2'b11;
end
end

else if(flag==2'b11)
begin
flag<=0;
b=~b;
end
end
endmodule

Edited by 0001lzb,a WHUer