xilinx常用buf

IBUFDS

差分输入buf，若DIFF_TERM设为TRUE，内部设置100欧终端电阻。

IBUFDS #(
   .DIFF_TERM("FALSE"),       // Differential Termination
   .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
)
IBUFDS_inst (
      .O(O),   // 1-bit output: Buffer output
      .I(I),   // 1-bit input: Diff_p buffer input (connect directly to top-level port)
      .IB(IB)  // 1-bit input: Diff_n buffer input (connect directly to top-level port)
);

IBUFDS_GTE2

IBUFDS_GTE2 #(
   .CLKCM_CFG("TRUE"),   // Refer to Transceiver User Guide
   .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
   .CLKSWING_CFG(2'b11)  // Refer to Transceiver User Guide
)
IBUFDS_GTE2_inst (
   .O(O),         // 1-bit output: Refer to Transceiver User Guide
   .ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
   .CEB(CEB),     // 1-bit input: Refer to Transceiver User Guide
   .I(I),         // 1-bit input: Refer to Transceiver User Guide
   .IB(IB)        // 1-bit input: Refer to Transceiver User Guide
);

---

OBUFDS

差分输出buf

OBUFDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I)      // Buffer input
);

---

BUFG

全局时钟buf，这个资源有限，在设计中很容易出现不够用的情况，在gt时钟部分可以适当复用或使用BUFH代替节省资源；在PLL设计中也可以适当去掉。（去掉Phase Alignment）

BUFG BUFG_inst (
      .O(O), // 1-bit output: Clock output
      .I(I)  // 1-bit input: Clock input
);

BUFG_GT

ultrascale系列gt bank使用

BUFG_GT BUFG_GT_inst (
      .O(O),             // 1-bit output: Buffer
      .CE(CE),           // 1-bit input: Buffer enable
      .CEMASK(CEMASK),   // 1-bit input: CE Mask
      .CLR(CLR),         // 1-bit input: Asynchronous clear
      .CLRMASK(CLRMASK), // 1-bit input: CLR Mask
      .DIV(DIV),         // 3-bit input: Dynamic divide Value
      .I(I)              // 1-bit input: Buffer
);

---

IOBUF

方法一：设置两个寄存器，一个用于保存输出值，一个用来控制输入还是输出。当inout口为输入时，设置为高阻状态即可。

module gtx_top(    
	input   sclk,    
	input   rst_n,   
	inout   sda
);
reg sdar;       //sda输出寄存器
reg sda_link;   //sda控制寄存器，0-input，1-output

assign sda = sda_link ? sdar : 1'bz;

方法二：使用原语，xilinx平台：

   // IOBUF: Single-ended Bi-directional Buffer
   //        All devices
   // Xilinx HDL Language Template, version 2018.3

   IOBUF #(
      .DRIVE(12), // Specify the output drive strength
      .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE" 
      .IOSTANDARD("DEFAULT"), // Specify the I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) IOBUF_inst (
      .O(O),     // Buffer output
      .IO(IO),   // Buffer inout port (connect directly to top-level port)
      .I(I),     // Buffer input
      .T(T)      // 3-state enable input, high=input, low=output
   );

管脚说明：以spi为例，O是IOBUF的输出端，也就是外部输入值，为sdin；IO为io复用脚；I为IOBUF的输入端，也就是内部输出值，为sdo；T在要读输入值时设为1。

IOBUF #(
  .DRIVE(12), // Specify the output drive strength
  .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE" 
  .IOSTANDARD("DEFAULT"), // Specify the I/O standard
  .SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
  .O(AF_SDI),     // Buffer output
  .IO(AF_SDIO),   // Buffer inout port (connect directly to top-level port)
  .I(AF_SDO),     // Buffer input
  .T(AF_T)      // 3-state enable input, high=input, low=output
);

---

IBUFDS_GTE3/4

ultrascale系列gt bank参考时钟输入buf



当bufg_gt有需要时，对于IBUFDS_GTE3/4只能链接ODIV2管脚
bufg_gt也可以连接txouclk / rxoutclk