【原创】基于Altera DE2的数字实验—001_1 （DE2）（Digital Logical）（Verilog）
DE2的基本使用技巧
本篇的3个实验包含DE2的拨动开关，数码管和七段码数码管显示的使用。前提，需要了解Quartus II的基本使用方法。
Project 1
通过拨动开关SW15-0设置一个16-bit的值，并将这个值通过按动KEY3显示在HEX3-0上。
project 1 code：
1
/*
File name : diglab1.v
2
* Functon : The user can set a 16-bit value using toggle switches 15-0 and transfer
3
* value to the first four hex digit displays by pressing KEY3.
4
* Author : JohnLoomis
5
*/
6
7
module
diglab1(
8
//
clock input (50 MHz)
9
input
CLOCK_50,
10
//
Push Buttons
11
input
[
3
:
0
] KEY,
12
//
DPDT Switches
13
input
[
17
:
0
] SW,
14
//
7-seg Displays
15
output
[
6
:
0
] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,
16
//
LEDS
17
output
[
8
:
0
] LEDG,
//
LED Green [8:0]
18
output
[
17
:
0
] LEDR,
//
LED Red[17:0]
19
//
GPIO Connections
20
inout
[
35
:
0
] GPIO_0, GPIO_1
21
);
22
23
//
set all inout port to tri-state
24
assign
GPIO_0
=
36
'
hzzzzzzzzz;
25
assign
GPIO_1
=
36
'
hzzzzzzzzz;
26
27
//
Connect dip switches to red LEDs
28
assign
LEDR[
17
:
0
]
=
SW[
17
:
0
];
29
30
//
turn off green LEDs
31
assign
LEDG[
8
:
0
]
=
0
;
32
33
wire
[
15
:
0
] A;
34
35
//
map to 7-segment displays
36
37
hex_7seg dsp0 (A[
3
:
0
], HEX0);
38
hex_7seg dsp1 (A[
7
:
4
], HEX1);
39
hex_7seg dsp2 (A[
11
:
8
], HEX2);
40
hex_7seg dsp3 (A[
15
:
12
], HEX3);
41
42
wire
[
6
:
0
] blank
=
~
7
'
h00;
43
44
//
blank remaining digits
45
assign
HEX4
=
blank;
46
assign
HEX5
=
blank;
47
assign
HEX6
=
blank;
48
//
assign HEX7 = blank;
49
assign
HEX7
=
~
SW[
6
:
0
];
50
51
//
control (set) value of A, signal with KEY3
52
53
//
always @(negedge KEY[3])
54
//
A <= SW[15:0];
55
56
assign
A
=
SW[
15
:
0
];
57
58
endmodule
59
60
/*
File name : hex_7seg.v
61
*/
62
63
module
hex_7seg (hex_digit, seg);
64
input
[
3
:
0
] hex_digit;
65
output
[
6
:
0
] seg;
66
reg
[
6
:
0
] seg;
67
//
seg = {g,f,e,d,c,b,a};
68
//
0 is on and 1 is off
69
70
always
@(hex_digit)
71
case
(hex_digit)
72
4
'
h0: seg = ~7
'
h3F;
73
4
'
h1: seg = ~7
'
h06;
//
---a----
74
4
'
h2: seg = ~7
'
h5B;
//
| |
75
4
'
h3: seg = ~7
'
h4F;
//
f b
76
4
'
h4: seg = ~7
'
h66;
//
| |
77
4
'
h5: seg = ~7
'
h6D;
//
---g----
78
4
'
h6: seg = ~7
'
h7D;
//
| |
79
4
'
h7: seg = ~7
'
h07;
//
e c
80
4
'
h8: seg = ~7
'
h7F;
//
| |
81
4
'
h9: seg = ~7
'
h67;
//
---d----
82
4
'
ha: seg = ~7
'
h77;
83
4
'
hb: seg = ~7
'
h7C;
84
4
'
hc: seg = ~7
'
h39;
85
4
'
hd: seg = ~7
'
h5E;
86
4
'
he: seg = ~7
'
h79;
87
4
'
hf: seg = ~7
'
h71;
88
endcase
89
90
endmodule
功能扩展
1. 直接将7个拨动开关的值映射到7-segment上显示。比如，用assign 语句：
assign HEX7 = ~SW[6:0];
这里有个小技巧，就是~SW[6:0]，因为查看DE2的用户手册可知，7-segment是低电平有效，这里取反，就好比负负 得正，可以直观显示SW的值。
2. 在HEX3-0上可编程显示：比如，显示HELP等。
3. 修改代码，用KEY3控制HEX7-6显示SW7-0的值A，用KEY2控制HEX5-4显示SW7-0的值B，用KEY1控制A，B相与，结果显示在HEX1-0，HEX3-2不显示。
3的参考代码：
1
/*
File name : diglab1_3.v
2
* Functon : KEY3 enters the 8-bit value (A) from SW[7:0] and displays it on HEX7-6, KEY2
3
* enters the 8-bit value (B) from SW[7:0] and displays it on HEX5-4, and KEY1
4
* generate the logical and of A and B and displays the result in HEX1-0. Blank
5
* the digits HEX3-2.
6
* Author : yf.x
7
* Copyleft: yf.x
8
*/
9
10
module
diglab1_3(
11
//
clock input (50 MHz)
12
input
CLOCK_50,
13
//
Push Buttons
14
input
[
3
:
1
] KEY,
15
//
DPDT Switches
16
input
[
7
:
0
] SW,
17
//
7-seg Displays
18
output
[
6
:
0
] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,
19
//
LEDS
20
output
[
8
:
0
] LEDG,
//
LED Green [8:0]
21
output
[
17
:
0
] LEDR,
//
LED Red[17:0]
22
//
GPIO Connections
23
inout
[
35
:
0
] GPIO_0, GPIO_1
24
);
25
26
//
set all inout port to tri-state
27
assign
GPIO_0
=
36
'
hzzzzzzzzz;
28
assign
GPIO_1
=
36
'
hzzzzzzzzz;
29
30
//
Connect dip switches to red LEDs
31
assign
LEDR[
7
:
0
]
=
SW[
7
:
0
];
32
33
//
turn off green LEDs
34
assign
LEDG[
8
:
0
]
=
0
;
35
36
reg
[
7
:
0
] A, B, C;
37
38
//
map to 7-segment displays
39
40
hex_7seg dsp0 (C[
3
:
0
], HEX0);
41
hex_7seg dsp1 (C[
7
:
4
], HEX1);
42
43
hex_7seg dsp7 (A[
7
:
4
], HEX7);
44
hex_7seg dsp6 (A[
3
:
0
], HEX6);
45
46
hex_7seg dsp5 (B[
7
:
4
], HEX5);
47
hex_7seg dsp4 (B[
3
:
0
], HEX4);
48
49
50
wire
[
6
:
0
] blank
=
~
7
'
h00;
51
52
//
blank remaining digits
53
assign
HEX3
=
blank;
54
assign
HEX2
=
blank;
55
56
//
control (set) value of A, signal with KEY3
57
58
always
@(
negedge
KEY[
3
])
59
A
<=
SW[
7
:
0
];
60
61
//
control (set) value of B, signal with KEY2
62
63
always
@(
negedge
KEY[
2
])
64
B
<=
SW[
7
:
0
];
65
66
//
control (set) value of C, signal with KEY1
67
68
always
@(
negedge
KEY[
1
])
69
C
<=
A
&
B;
70
71
72
endmodule
73
参考
1. John Loomis，digitallab1.