「HDLBits题解」CS450

本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

---

题目链接：Cs450/timer - HDLBits

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
    reg [9:0] cnt ; 

    always @ (posedge clk) begin 
        if (load) cnt <= data ; 
        else cnt <= cnt == 0 ? 0 : cnt - 1; 
    end

    assign tc = cnt == 0 ;

endmodule

---

题目链接：Cs450/counter 2bc - HDLBits

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output reg [1:0] state
);
    always @(posedge clk or posedge areset) begin
        if (areset) state <= 2'b01 ; 
        else if (train_valid) 
            if (train_taken) state <= state == 2'b11 ? 2'b11 : state + 1 ; 
            else state <= state == 2'b00 ? 2'b00 : state - 1 ; 
        else 
            state <= state ; 
    end

endmodule

---

题目链接：Cs450/history shift - HDLBits

module top_module(
    input clk,
    input areset,

    input predict_valid,
    input predict_taken,
    output [31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);
    reg [31:0] history ; 

    assign predict_history = history ; 

    always @(posedge clk or posedge areset) begin
        if (areset) history <= 32'b0 ; 
        else if (train_mispredicted) history <= {train_history[30:0], train_taken} ; 
        else if (predict_valid) history <= {history[30:0], predict_taken} ; 
        else history <= history ; 
    end

endmodule

---

题目链接：Cs450/gshare - HDLBits

module top_module(
    input clk,
    input areset,

    input  predict_valid,
    input  [6:0] predict_pc,
    output predict_taken,
    output [6:0] predict_history,

    input train_valid,
    input train_taken,
    input train_mispredicted,
    input [6:0] train_history,
    input [6:0] train_pc
);
    reg [1:0] PHT[127:0];
    integer i;
    always @(posedge clk, posedge areset) begin
        if (areset) begin
            predict_history <= 0;
            for (i=0; i<128; i=i+1) PHT[i] <= 2'b01;
        end
        else begin
            if (train_valid && train_mispredicted)
                predict_history <= {train_history[5:0], train_taken};
            else if (predict_valid)
                predict_history <= {predict_history[5:0], predict_taken};
            
            if (train_valid) begin
                if (train_taken)
                    PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b11) ? 2'b11 : (PHT[train_history ^ train_pc] + 1);
            else
                    PHT[train_history ^ train_pc] <= (PHT[train_history ^ train_pc] == 2'b00) ? 2'b00 : (PHT[train_history ^ train_pc] - 1);
            end
        end
    end
    assign predict_taken = PHT[predict_history ^ predict_pc][1];
endmodule