~Datasheet - MemoryController

sdram介绍：

SDRAM从发展到现在已经经历了四代，分别是：

第一代SDR SDRAM，

第二代DDR SDRAM，

第三代DDR2 SDRAM，

第四代DDR3 SDRAM.

(显卡上的DDR已经发展到DDR5)

 

--工作电压--

　　SDR：3.3V，   DDR：2.5V，   DDR2：1.8V，   DDR3：1.5V

 

配置要点：

刷新周期的计算：

Refresh period = (211-refresh_count+1)/HCLK



Ex) If refresh period is 7.8 us and HCLK is 100MHz,



the refresh count is as follows:



Refresh count = 211 + 1 - 100x7.8 = 1269

 

内存的DATA BIT：

8bit, 16bit, 32bit...

 

时序，比如：（具体以内存的datasheet为主）

　

CAS latency ：

一般是3～5。

CAS

      内存的CAS延迟时间和存取时间之间有着密切的联系。首先解释一下什么是内存的CAS延迟时间。所谓CAS延迟时间，就是指内存纵向地址脉冲的反应时间。CAS延迟时间是在一定频率下衡量支持不同规范内存的重要标志之一。在Intel公司的PC100内存技术白皮书中指出：“符合PC100标准的内存芯片应该以CAS Latency（以下简称CL）= 2的情况稳定工作在100MHZ的频率下。”CL=2所表示的意义是此时内存读取数据的延迟时间是两个时钟周期当CL=3时。内存读取数据的延迟时间就应该是三个时钟周期，因此，这“2”与“3”之间的差别就不仅仅局限于“1”了，而是1个时钟周期。工作在相同频率下的同种内存，将CL设置为2会得到比3更优秀的性能（当然你的内存必须支持CL=2的模式）。为了使主板正确地为内存设定CAS延迟时间，内存生产厂商都将其内存在不同工作频率下所推荐的CAS延迟时间记录在了内存PCB板上的一块EEPROM上，这块芯片就是我们所说的SPD。当系统开机时，主板BIOS会自动检测SPD中的信息并最终确定是以CL=2还是CL=3来运行。

 

 

 

2440的配置:

BWSCON = (0x2 << 24);



BANKCON6 = 1 | (2 << 2) | (7 << 8) | (3 << 11) | (3 << 15);



REFRESH = (1269) | (3 << 18) | (2 << 20) | (1 << 23);



BANKSIZE = 1 | (1 << 4) | (1 << 5) | (1 << 7);



MRSRB6 = (3 << 4);

 

2416的配置：

The S3C2416 Mobile DRAM Controller supports three kinds of memory interface - (Mobile) SDRAM and mobile DDR and DDR2.

Mobile DRAM controller provides 2 chip select signals (2 memory banks), these are used for up to 2 (mobile) SDRAM banks or 2 mobile DDR banks or 2 DDR2 banks.

Mobile DRAM controller can’t support 3 kinds of memory interface simultaneous, for example one bank for (mobile) SDRAM and one bank for mobile DDR.

Address space: up to 128Mbyte

 

DDR2 Features

− Support DDR2 having architecture, don’t support 8-bank architecture.

− Support external data bus interface

− Support AL(Additive Latency) 0, don’t support posted CAS, .

− Don’t support ODT and nDQS function, it needs EMRS setting.

− All other features are same to the features of SDR/mDDR

 

ddr2的工作原理，及其特点

datasheet给面子，有详细的步骤。

ddr2初始化：

DDR2 INITIALIZATION SEQUENCE

1. Setting the BANKCFG & BANKCON1, 2, 3

2. Wait 200us to allow DRAM power and clock stabilize.

3. Wait minimum of 400 ns then issue a PALL(pre-charge all) command.

Program the INIT[1:0] to ‘01b’. This automatically issues a PALL(pre-charge all) command to the DRAM.

4. Issue an EMRS command to EMR(2), provide LOW to BA0, High to BA1.

Program the INIT[1:0] of Control Register1 to ‘11b’ & BANKCON3[31]=’1b’

5. Issue an EMRS command to EMR(3), provide High to BA0 and BA1.

Program the INIT[1:0] of Control Register1 to ‘11b’ & BANKCON3[31:30]=’11b’

6. Issue an EMRS to enable DLL and RDQS, nDQS, ODT disable.

7. Issue a Mode Register Set command for DLL reset.(To issue DLL Reset command, provide HIGH to A8 and

LOW to BA0-BA1, and A13-A15.) Program the INIT[1:0] to ‘10b’. & BANKCON3[8]=’1b’

8. Issue a PALL(pre-charge all) command.

Program the INIT[1:0] to ‘01b’. This automatically issues a PALL(pre-charge all) command to the DRAM.

9. Issue 2 or more auto-refresh commands.

10. Issue a MRS command with LOW to A8 to initialize device operation.

Program the INIT[1:0] to ‘10b’. & BANKCON3[8]=’0b’

11. Wait 200 clock after step 7, execute OCD Calibration.

12. The external DRAM is now ready for normal operation

 

参考uboot配置，比如：

– cpu/s3c24xx/s3c2416/cpu_init.S --




sdr_ctrl_asm_init: Initialize memory controller



/* boyko : Memory Type DDR2 */



1004: ldr r4, =ELFIN_MEMCTL_BASE



/* Step 1: BANKCFG Setting */



ldr r2, =CFG_BANK_CFG_VAL_DDR2



str r2, [r4, #BANKCFG_OFFSET]



ldr r2, =0x44000040



str r2, [r4, #BANKCON1_OFFSET]



/* Step 2: BANKCON2 Setting */



ldr r2, =CFG_BANK_CON2_VAL_DDR2



str r2, [r4, #BANKCON2_OFFSET]



/* Step 3: issue PALL */



orr r2, r1, #INIT_PALL



str r2, [r4, #BANKCON1_OFFSET]



/* Step 4: Issue a EMRS2 command */



ldr r2, =0x80000000



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_EMRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 5: Issue a EMRS3 command */



ldr r2, =0xc0000000



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_EMRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 6: Issue a EMRS1 command */



ldr r2, =0x44000000



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_EMRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 7: issue MRS */



ldr r2, =0x44000130



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_MRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 8: issue PALL */



orr r2, r1, #INIT_PALL



str r2, [r4, #BANKCON1_OFFSET]



/* Step 9: write 0xff into the refresh timer */



mov r3, #0xff



str r3, [r4, #REFRESH_OFFSET]



/* Step 10: wait more than 120 clk */



mov r3, #0x100



10: subs r3, r3, #1



bne 10b



/* Step 11: issue MRS */



ldr r2, =0x44000030



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_MRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 12: Issue a EMRS1 command */



ldr r2, =0x47800030



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_EMRS



str r2, [r4, #BANKCON1_OFFSET]



ldr r2, =0x44000030



str r2, [r4, #BANKCON3_OFFSET]



orr r2, r1, #INIT_EMRS



str r2, [r4, #BANKCON1_OFFSET]



/* Step 13: write 0x87 into the refresh timer */



mov r3, #0x87



str r3, [r4, #REFRESH_OFFSET]



/* Step 14: Normal Mode */



orr r2, r1, #INIT_NORMAL



str r2, [r4, #BANKCON1_OFFSET]



/* boyko : Memory Type DDR2 */

 

 

 

http://hi.baidu.com/kebey2004/item/9127c421676bff47469962a5