latch 与 dff 在电路上的区别

dff:

module d_ff (
  input      clk,
  input      rst_n,
  input      en,
  input      d,
  output reg q
);

always @ (posedge clk or negedge rst_n)
  if (!rst_n)
    q <= 0;
  else if (en)
    q <= d;
endmodule

 

latch

module lat(Q, QBar, D, clk, rst_); // level-triggered latch behavioral model
input D,clk,rst_;
output Q, QBar;
reg Q;
wire QBar;
always @(clk or rst_ or D)
begin
if(!rst_) Q=1'b0;
else if(clk)Q=D;
end
assign QBar = ~Q;
endmodule