【笔记】5502 DSP reset序列（ Reset Sequence）

根据5502 Datasheet翻译，原文见Datasheet 3.9.6节

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3.9.6  复位序列

当RESET#信号为低（LOW）时，时钟发生器进入旁路模式（bypass mode），此时根据GPIO4的状态的不同，输入时钟被置为CLKIN或X2/CLKIN。当RESET#管脚的电平由低转高时，以下事件将会按照下列顺序依次进行。

• GPIO6和GPIO7在reset信号的上升沿时刻被采样。GPIO6和GPIO7的状态决定了5502复用引脚的功能，（详见5502 datasheet 3.3节，可配置的外部端口和信号）。GPIO6和GPIO7的在reset上升沿时的状态分别决定了外部总线控制寄存器（External Bus Control Register ，XBSR）中Parallel/Host Port Mux Mode bit以及Serial Port 2 Mux Mode bit的值。
• GPIO4在reset信号的上升沿时刻被采样，它的状态将被用来设置始终模式控制寄存器（Clock Mode Control Register，CLKMD）的CLKMD0 位，该位用来决定DSP的时钟源。CLKMD0位选择内部振荡器输出（internal oscillator output ，OSCOUT）或X2/CLKIN管脚为DSP的输入时钟源。如果在reset时，GPIO4为低电平，则CLKMD0位被置为0，此时内部振荡器和外部的晶体将为DSP生成输入时钟。如果在reset时，GPIO4为高电平，则CLKMD0位将被置为1，且输入时钟将直接由X2/CLKIN管脚提供。
• 当reset信号由低变高时，DSP不会马上从reset的状态中结束。事实上，一个内部的计数器（internal counter）会计数41032个时钟周期来让内部振荡器状态稳定（只在GPIO4位低电平状态下发生）。另外，内部计数器还会增加70个参考时钟周期来让reset信号传播到设备的不同部分中。
• 当所有的内部延迟周期都完成后，BOOTM[2:0]管脚将被采样，并且它们的值将被存储在引导模式寄存器（Boot Mode Register，BOOTM_MODE）中。BOOTM_MODE寄存器中的值将被bootloader用来决定DSP的引导模式。
• 程序流将在所有的内部延迟周期结束后开始。

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原文

3.9.6 Reset Sequence
When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or X2/CLKIN,
dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the following events
will occur in the order listed below.
• GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. The state of GPIO6 and GPIO7
determines the function of the multiplexed pins of the 5502, see Section 3.3, Configurable External Ports
and Signals, for more information on pin multiplexing. The state of GPIO6 and GPIO7 during the rising
edge of reset determines the values for the Parallel/Host Port Mux Mode and the Serial Port 2 Mux Mode
bits, respectively, of the External Bus Control Register (XBSR).
• GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock
Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0
bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source
for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal oscillator and the
external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to 1 and
the input clock will be taken directly from the X2/CLKIN pin.
• After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately.
Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize (only
if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset signal
to propagate through different parts of the device.
• After all internal delay cycles have expired, the BOOTM[2:0] pins will be sampled and their values will be
stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE register will be used
by the bootloader to determine the boot mode of the DSP.
• Program flow will commence after all internal delay cycles have expired.