CY7C131 BUSY信号线的接法

在考虑双口RAM的读写冲突问题时，决定使用双口RAM CY7C131的BUSY信号线来对FT2232H的MCU Host Bus进行反馈。

当双口RAM的某个单元可读写时，BUSYL和BUSYR都是High电平，如果发生冲突，那么其中迟来的一个请求会变成Low电平。

此时，有两种思路。

(一)依靠BUSY线连接MCU Host Bus的I/01 管脚进行监听

MCU Host Bus的I/01 管脚的描述如下：

Pin No.	Name	Type	Fast Serial Interface Configuration Description
46	I/O1	I/O	MPSSE mode instructions to set / clear or read the high byte of data can be used with this pin. In addition this pin has instructions which will make the controller wait until it is high, or wait until it is low. This can be used to connect to an IRQ pin of a peripheral chip. The FT2232H will wait for the interrupt, and then read the device, and pass the answer back to the host PC. I/O1 must be held in input mode if this option is used. Please refer to Application Note AN_108 for operation of these instructions.

该管脚的使用方法在文档AN_108 中的描述如下：

5.2 Wait On I/O High 0x88, This will cause the MPSSE controller to wait until GPIOL1 (JTAG) or I/O1 (CPU) is high. Once it is detected as high, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes high.

5.3 Wait On I/O Low 0x89, This will cause the controller to wait until GPIOL1 (JTAG) or I/O1 (CPU) is low. Once it is detected as low, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes low.

思路：

由于在没有冲突的状态下BUSY输出为High，所以，可以将I/O1设置在wait on High的状态上，当满足I/O1管脚接收到的电平为高电平这一要求时，才执行下一条指令（可将读写指令设置为等待高电平后的下一条指令）。这样一来，当产生读写冲突时，如果我方被置为BUSY低电平，即我方是被抑制读写的一方，那么我方程序将等待对方读写完成后，将我方的BUSY回复为高电平时才进行读写。如此可以避免读写冲突。

（二）使用BUSY信号接IORDY管脚延长读写时间

观察MCU HOST BUS EMULATION 模式的读写时序，如下

可知，在DIV BY 5处于On状态时，IORDY在Low电平和High电平下，t5周期相差很大。

由此，可利用双口RAM的BUSY端接MCU HOST BUS的IORDY管脚，在该端