OMAPL138串口烧写UBL、UBOOT问题

问题：

我使用sfh_OMAP-L138.exe串口烧写工具来烧写UBL、UBOOT时，在擦除的过程中总是停止在Waiting for SFT on the OMAP-L138...这，具体信息如下：

C:\temp>sfh_OMAP-L138.exe -erase -targetType OMAPL138 -flashType NAND -P COM4
-----------------------------------------------------
   TI Serial Flasher Host Program for OMAP-L138
   (C) 2010, Texas Instruments, Inc.
   Ver. 1.67
-----------------------------------------------------

      [TYPE] Global erase
    [TARGET] OMAPL138
    [DEVICE] NAND

Attempting to connect to device COM4...
Press any key to end this program at any time.

(AIS Parse): Read magic word 0x41504954.
(AIS Parse): Waiting for BOOTME... (power on or reset target now)
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word Sync...
(AIS Parse): Performing Ping Opcode Sync...
(AIS Parse): Processing command 0: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 13512-Byte section to address 0x80000000.
(AIS Parse): Processing command 1: 0x58535901.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Loading section...
(AIS Parse): Loaded 1360-Byte section to address 0x800034C8.
(AIS Parse): Processing command 2: 0x58535906.
(AIS Parse): Performing Opcode Sync...
(AIS Parse): Performing jump and close...
(AIS Parse): AIS complete. Jump to address 0x80000000.
(AIS Parse): Waiting for DONE...
(AIS Parse): Boot completed successfully.

Waiting for SFT on the OMAP-L138...

请问这是什么原因，怎么解决呢？

回答：

请问你是在EVM板还是自己的板上测试的？因为官方的EVM板子上面用的mDDR，如果你用的DDR2的话，需要改动sft工具。在device.c中，你可以改动最后一个mDDR的配置为DDR2的配置。配置的方法可以参考mDDR/DDR2 controller user guide。

Uint32 DEVICE_init()

{

 Uint32 status = E_PASS;

 // Ensure the kick registers are unlocked

 // Note these lines have no effect on 2.0 and later silicon

 DEVICE_kickLock();

 DEVICE_kickUnlock();

 SYSTEM->SUSPSRC &= ( (1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16));

#ifndef SKIP_LOW_LEVEL_INIT

 // System PSC Setup

 DEVICE_PSCInit();

 // System PLL Setup

 if (status == E_PASS)

 {

 #if defined(AM1808)

   // CPU(s) at 456 MHz

   status |= DEVICE_PLL0Init(0, 18, 0, 0, 0, 18, 8);

 #else

   // CPU(s) at 300 MHz

   status |= DEVICE_PLL0Init(0, 24, 0, 1, 0, 11, 5);

 #endif  

 }

 if (status == E_PASS)

 {

   // mDDR @ 150MHz

   status |= DEVICE_PLL1Init(24, 1, 0, 1, 2);

 }

 // External Memory Timing Setup

 if (status == E_PASS)

 {

   // Timings for mDDR at 150 MHz

   status |= DEVICE_ExternalMemInit(0x000000C4, 0x0A034622, 0x1C912A08, 0x3811C700, 0x00000494, 0x00000000);

 }

#endif

 return status;