千兆网(1):IDDR 原语 RX 测试
//——————————————————
说明:
板卡平台: 米联客 SPARTAN6 MiS607
PHY芯片手册:VSC8601XKN
//——————————————————-
RX接口输入信号
信号名称
RX_CLK : 同步时钟125Mhz
RX_DATA : 双沿数据
RX_DV : 数据有效信号，双沿
接口时序
查看原语手册
1. spartan6 selectIo
2. spartan6_hdl
测试代码实现(参考)
//RX-FPGA接收端
//处理网口发来的数据包
/*------------------.ucf------------------------
NET "rx_clk" LOC = E16; //PHY_RXCLK
NET "rx_dv" LOC = C18; //PHY_RX_CTL
NET "rx_data[3]" LOC = G16; //PHY_RX_D3
NET "rx_data[2]" LOC = F17; //PHY_RX_D2
NET "rx_data[1]" LOC = C17; //PHY_RX_D1
NET "rx_data[0]" LOC = A17; //PHY_RX_D0
-----------------------------------------------*/
module RGMII_rx_ctrl (
//from phy
input wire rx_clk, //125M
input wire rst_n,
input wire rx_dv,//千兆网同步有效信号,双沿采样 上升沿=dv 下降沿=deer
input wire [3:0]rx_data,
//to mac //物理层
output reg rx_en,
output reg [7:0]o_data//单沿采样数据
);
wire tmp_dv;
wire tmp_err;//rxdv,rxerr
wire [7:0]tmp_data;
//例化5次,一次使能,4次数据
// IDDR2: Input Double Data Rate Input Register with Set, Reset
// and Clock Enable.
// Spartan-3E/3A/6
// Xilinx HDL Libraries Guide, version 11.2
IDDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
)
//in order to : input rx_dv; output rx_en;
IDDR2_inst (//tmp_dv=rx_en,产生一位rx_en信号的
.Q0(tmp_dv), // 1-bit output captured with C0 clock
.Q1(tmp_err), // 1-bit output captured with C1 clock
.C0(rx_clk), // 1-bit clock input
.C1(~rx_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
//----------------------------------------
.D(rx_dv), // 1-bit DDR data input
//--------------------------------------
.R(1'b0), // 1-bit reset input
.S(~rst_n) // 1-bit set input
);
// End of IDDR2_inst instantiation
genvar i;
generate
for(i=0;i<4;i=i+1)begin
IDDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
)
IDDR2_inst_r (//产生8位数据模块
.Q0(tmp_data[i]), // 1-bit output captured with C0 clock
.Q1(tmp_data[i+4]), // 1-bit output captured with C1 clock
.C0(rx_clk), // 1-bit clock input
.C1(~rx_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(rx_data[i]), // 1-bit DDR data input
.R(1'b0), // 1-bit reset input
.S(~rst_n) // 1-bit set input
);
end
endgenerate
always @(posedge rx_clk)
if(!rst_n)
o_data <= 'd0;
else
o_data <= tmp_data;
always @(posedge rx_clk)
if(!rst_n)
rx_en <= 'd0;
else
rx_en <= tmp_dv;
endmoduletop
/*------------------.ucf------------------------
NET "sclk" LOC = Y13;
NET "rst_n" LOC = J7;
NET "phy_rst_n" LOC = C19; //PHY_Rst#
NET "rx_clk" LOC = E16; //PHY_RXCLK
NET "rx_dv" LOC = C18; //PHY_RX_CTL
NET "rx_data[3]" LOC = G16; //PHY_RX_D3
NET "rx_data[2]" LOC = F17; //PHY_RX_D2
NET "rx_data[1]" LOC = C17; //PHY_RX_D1
NET "rx_data[0]" LOC = A17; //PHY_RX_D0
-----------------------------------------------*/
module top_RGMII(
input wire sclk,
input wire rst_n,
//
input wire rx_clk,
input wire rx_dv,
input wire [3:0]rx_data,
output wire phy_rst_n,
output wire tout
);
reg [21:0]rst_cnt;
wire [7:0]o_data;
wire rx_en;
assign tout = rx_en|(&o_data);//for test
always @(posedge sclk)
if(!rst_n)
rst_cnt <= 'd0;
else if(rst_cnt[21]== 'd0)
rst_cnt <= rst_cnt + 'd1;
assign phy_rst_n = rst_cnt[21];//上电复位延时大于4ms
RGMII_rx_ctrl RGMII_rx_ctrl_inst(
//from phy
.rx_clk(rx_clk), //125M
.rst_n(rst_n),
.rx_dv(rx_dv),//千兆网同步有效信号,双沿采样 上升沿=dv 下降沿=deer
.rx_data(rx_data),
.rx_en(rx_en),
.o_data(o_data)//单沿采样数据
);
endmoduleChipscope抓取波形图:
详情请查看手册要求
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小怪物千兆网笔记