Verilog设计四进位比较器的代码

主电路
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/05/29 16:07:24
// Design Name:
// Module Name: n_bit_comparator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module n_bit_comparator(A,B,equal,greater,less);
parameter n=4;
input[n-1:0]A;
input[n-1:0]B;
output equal;
output greater;
output less;
wire [n-1:0]A_e;
wire [n-1:0]A_g;
wire [n-1:0]A_l;
wire [n-1:0]B_e;
wire [n-1:0]B_g;
wire [n-1:0]B_l;
assign A_e[0]=(A[0]&B[0])|((_A[0])&(B[0]));
assign A_g[0]=(A[0]&(~B[0]));
assign A_l[0]=(B[0]&(~A[0]));
assign A_e[1]=(A[1]&B[1])|((_A[1])&(B[1]));
assign A_g[1]=(A[1]&(~B[1]));
assign A_l[1]=(B[1]&(~A[1]));
assign A_e[2]=(A[2]&B[2])|((_A[2])&(B[2]));
assign A_g[2]=(A[2]&(~B[2]));
assign A_l[2]=(B[2]&(~A[2]));
assign A_e[3]=(A[3]&B[3])|((_A[3])&(B[3]));
assign A_g[3]=(A[3]&(~B[3]));
assign A_l[3]=(B[3]&(~A[3]));

assign B_e[0]=A_e[3];
assign B_g[0]=A_g[3];
assign B_l[0]=A_l[3];

assign B_e[1]=A_e[3]&A_e[2];
assign B_g[1]=B_g[0]|(A_e[3]&A_g[2]);
assign B_l[1]=B_l[0]|(A_e[3]&A_l[2]);

assign B_e[2]=A_e[3]&A_e[2]&A_e[1];
assign B_g[2]=B_g[1]|(A_e[3]&A_e[2]&A_g[1]);
assign B_l[2]=B_l[1]|(A_e[3]&A_e[2]&A_l[1]);

assign B_e[3]=A_e[3]&A_e[2]&A_e[1]&A_e[0];
assign B_g[3]=B_g[2]|(A_e[3]&A_e[2]&A_e[1]&A_g[0]);
assign B_l[3]=B_l[2]|(A_e[3]&A_e[2]&A_e[1]&A_l[0]);

assign equal=B_e[3];
assign greater=B_g[3];
assign less=B_l[3];

endmodule

测试电路：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/05/29 16:08:07
// Design Name:
// Module Name: test_comparator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test_comparator();
reg [3:0]A;
reg [3:0]B;
wire equal;
wire greater;
wire less;
n_bit_comparator utt(.A(A),.B(B),.equal(equal),.greater(greater),.less(less));
initial
begin
A=0;
B=0;
#100 KaTeX parse error: Expected 'EOF', got '#' at position 20: …sh; end always #̲5 begin A=random;
B=$random;
end
endmodule