verilog脉冲产生高电平

本模块输入一个脉冲，产生一个持续一段时间的高电平，系统时钟为10M，高电平持续时间为100us。
先将pulse信号进行打一拍操作，检测上升沿，然后用一个计数器控制高电平保持时间~

module pulse_test(
    input   wire    sclk,
    input   wire    rst_n,
    input   wire    pulse,
    output  wire    highleavel
);

reg     pulse_dly;
reg [9:0]   cnt;
reg     highleavel_reg;

always @(posedge sclk)
    pulse_dly <= pulse;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        cnt <= 'd0;
    else if(pulse == 1'b1 && pulse_dly == 1'b0)
        cnt <= 'd0;
    else if(cnt == 'd999)
        cnt <= 'd0;
    else
        cnt <= cnt + 'd1;

always @(posedge sclk or negedge rst_n)
    if(rst_n == 1'b0)
        highleavel_reg <= 1'b0;
    else if(pulse == 1'b1 && pulse_dly == 1'b0)
        highleavel_reg <= 1'b1;
    else if(cnt == 'd999)
        highleavel_reg <= 1'b0;
    else
        highleavel_reg <= highleavel_reg;

assign highleavel = highleavel_reg;

endmodule

仿真波形如下：

testbench代码如下：

`timescale 1ns / 1ns

module tb_pulse_test();
reg     sclk;
reg     rst_n;
reg     pulse;

initial begin
    sclk    = 0;
    rst_n   = 0;
    #100
    rst_n   = 1;
    pulse   = 0;
end

always #50  sclk = ~sclk;
always #100000  gen_pulse();

task    gen_pulse();
    integer i;
    begin
        for(i=0;i<5;i=i+1)
        begin
            @(posedge sclk)
            pulse <= 1'b1;
        end
        pulse   <= 1'b0;    
    end

endtask


pulse_test pulse_test_inst(
    .sclk           (sclk),
    .rst_n          (rst_n),
    .pulse          (pulse),
    .highleavel     (highleavel)
);
endmodule

封装好的IP核仿真通过后tb文件一定要另存，否则package ip后tb文件直接找不到了！！！