[RK3399][Android7.1] 调试笔记 --- 系统默认时钟配置
OS: Android 7.1
Board: Firefly-RK3399
Kernel: v4.4.55
分两个模块，一个是cpu，还有一个是pmu模块，这里只举例cpu,cpu又分在两个文件中定义。
rk3399.dtsi:
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
<&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_GPU>, <&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
assigned-clock-rates =
<400000000>, <200000000>,
<400000000>, <200000000>,
<816000000>, <816000000>,
<594000000>, <800000000>,
<200000000>, <1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>,
<100000000>, <50000000>;
};rk3399-vop-clk-set.dtsi:
&cru {
assigned-clocks =
<&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
<&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>,
<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
<&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
<&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
<&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_NPLL>, <&cru ACLK_GPU>,
<&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
<&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
<&cru PCLK_PERILP1>, <&cru SCLK_I2C1>,
<&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
<&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
<&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
<&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
<&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
<&cru ACLK_GIC>, <&cru ACLK_ISP0>,
<&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
<&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
<&cru ACLK_HDCP>, <&cru ACLK_VIO>,
<&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
<&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
<&cru ACLK_IEP>, <&cru ACLK_RGA>,
<&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
<&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
<&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
<&cru FCLK_CM0S>, <&cru ACLK_CCI>,
<&cru PCLK_ALIVE>, <&cru SCLK_CS>,
<&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
assigned-clock-rates =
<75000000>, <50000000>,
<50000000>, <50000000>,
<50000000>, <100000000>,
<50000000>, <150000000>,
<150000000>, <150000000>,
<50000000>, <150000000>,
<50000000>, <100000000>,
<75000000>, <75000000>,
<816000000>, <816000000>,
<600000000>, <200000000>,
<800000000>, <150000000>,
<75000000>, <37500000>,
<100000000>, <100000000>,
<50000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<100000000>, <100000000>,
<100000000>, <50000000>,
<50000000>, <50000000>,
<50000000>, <50000000>,
<200000000>, <400000000>,
<400000000>, <100000000>,
<100000000>, <100000000>,
<400000000>, <400000000>,
<200000000>, <100000000>,
<200000000>, <200000000>,
<100000000>, <400000000>,
<400000000>, <400000000>,
<400000000>, <300000000>,
<400000000>, <200000000>,
<400000000>, <300000000>,
<300000000>, <300000000>,
<300000000>, <300000000>,
<100000000>, <150000000>,
<150000000>, <400000000>,
<100000000>, <400000000>,
<100000000>;
};assigned-clocks的id和assigned-clock-rates值一一对应。
assigned-clock-rates对应的值会在cru驱动初始化时设置:
rk3399_clk_init -> clk-rk3399.c
rockchip_clk_of_add_provider -> clk.c
of_clk_add_provider ->
of_clk_set_defaults -> clk-conf.c
__set_clk_rates__set_clk_rates():
static int __set_clk_rates(struct device_node *node, bool clk_supplier)
{
......
of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
if (rate) {
rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, &clkspec);
......
clk = of_clk_get_from_provider(&clkspec);
......
rc = clk_set_rate(clk, rate);
......
index++;
}
return 0;
}还有一部分已经在loader或者uboot中配置好了，只要直接读取即可，例如ddr的clock.
可参见： [RK3399][Android7.1] 调试笔记 — DDR工作频率的获取和设置