使用Cordic算法实现FPGA上的指数计算

最近做的内容用到了指数运算，虽然Xilinx提供了指数运算的ip核，但还是决定自己写一个关于指数运算的Verilog代码。在fpga上实现指数运算主要有两种方式，一种是使用查找表，另外一种是使用cordic算法，这里选择使用cordic旋转双曲坐标得到指数计算的近似值。
先补一下coedic的原理，引用一篇blog，已经说的很详细了:
https://blog.csdn.net/u010712012/article/details/77755567
下面就直接上Verilog代码，10级流水线：

module Exp_full(clk,rst_n,Inputdata,InputEN,OutputData);
input clk;
input rst_n;
input signed [15:0]Inputdata;
input InputEN;
output signed [15:0] OutputData;


reg signed [15:0] angel [9:0];
parameter signed An=16'b0001001101000111;//16'b0001001101010010;
                  
				  
always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
		angel[0]<=16'b0000100011001010;// 0.549306,1/2
        angel[1]<=16'b0000010000010110;//0.255413,1/4
        angel[2]<=16'b0000001000000011;//0.125657,1/8
        angel[3]<=16'b0000000100000000;//0.062582,1/16
        angel[4]<=16'b0000000100000000;//,1,2,3,4,4,5,6,
        angel[5]<=16'b0000000010000000;//0.031260
        angel[6]<=16'b0000000001000000;//0.015626
        angel[7]<=16'b0000000000100000;//0.007813
	    angel[8]<=16'b0000000000010000;//0.003906250
        angel[9]<=16'b0000000000001000;//0.001953125
	end
end


reg signed [15:0] x [10:0];
reg signed [15:0] y [10:0];
reg signed [15:0] z [10:0];

always@(posedge clk or negedge rst_n)   //initial
begin
	if(rst_n!=1)
	begin
	x[0]<= 16'b0;
	y[0]<=  16'b0;
	z[0]<=16'b0;
	end
	else 
	begin
			x[0]<= An;
			y[0]<=$signed (16'b0);
		if(InputEN)
		begin	
			z[0]<=$signed (Inputdata);//data_in;
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[1]<=$signed (16'b0);
	y[1]<=$signed (16'b0);
	z[1]<=$signed (16'b0);
	end
	else
	begin
		if(z[0][15])
		begin
			x[1]<=$signed (x[0])-( $signed (y[0])>>>1);
			y[1]<=$signed (y[0])-($signed (x[0])>>>1);
			z[1]<=z[0]+angel[0];
		end
		else
		begin
			x[1]<=$signed (x[0])+($signed (y[0])>>>1);
			y[1]<=$signed (y[0])+($signed (x[0])>>>1);
			z[1]<=z[0]-angel[0];
		end
	end
end


always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[2]<=16'b0;
	y[2]<=16'b0;
	z[2]<=16'b0;
	end
	else
	begin
		if(z[1][15])
		begin
			x[2]<=$signed (x[1])-($signed (y[1])>>>2);
			y[2]<=$signed (y[1])-($signed (x[1])>>>2);
			z[2]<=z[1]+angel[1];
		end
		else
		begin
			x[2]<=$signed (x[1])+($signed (y[1])>>>2);
			y[2]<=$signed (y[1])+($signed (x[1])>>>2);
			z[2]<=z[1]-angel[1];
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[3]<=16'b0;
	y[3]<=16'b0;
	z[3]<=16'b0;
	end
	else
	begin
		if(z[2][15])
		begin
			x[3]<=$signed (x[2])-($signed (y[2])>>>3);
			y[3]<=$signed (y[2])-($signed (x[2])>>>3);
			z[3]<=z[2]+angel[2];
		end
		else
		begin
			x[3]<=$signed (x[2])+($signed (y[2])>>>3);
			y[3]<=$signed (y[2])+($signed (x[2])>>>3);
			z[3]<=z[2]-angel[2];
		end
	end
end


always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[4]<=16'b0;
	y[4]<=16'b0;
	z[4]<=16'b0;
	end
	else
	begin
		if(z[3][15])
		begin
			x[4]<=$signed (x[3])-($signed (y[3])>>>4);
			y[4]<=$signed (y[3])-($signed (x[3])>>>4);
			z[4]<=z[3]+angel[3];
		end
		else
		begin
			x[4]<=$signed (x[3])+($signed (y[3])>>>4);
			y[4]<=$signed (y[3])+($signed (x[3])>>>4);
			z[4]<=z[3]-angel[3];
		end
	end
end


always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[5]<=16'b0;
	y[5]<=16'b0;
	z[5]<=16'b0;
	end
	else
	begin
		if(z[4][15])
		begin
			x[5]<=$signed (x[4])-($signed (y[4])>>>5);
			y[5]<=$signed (y[4])-($signed (x[4])>>>5);
			z[5]<=z[4]+angel[4];
		end
		else
		begin
			x[5]<=$signed (x[4])+($signed (y[4])>>>5);
			y[5]<=$signed (y[4])+($signed (x[4])>>>5);
			z[5]<=z[4]-angel[4];
		end
	end
end


always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[6]<=16'b0;
	y[6]<=16'b0;
	z[6]<=16'b0;
	end
	else
	begin
		if(z[5][15])
		begin
			x[6]<=$signed (x[5])-($signed (y[5])>>>6);
			y[6]<=$signed (y[5])-($signed (x[5])>>>6);
			z[6]<=z[5]+angel[5];
		end
		else
		begin
			x[6]<=$signed (x[5])+($signed (y[5])>>>6);
			y[6]<=$signed (y[5])+($signed (x[5])>>>6);
			z[6]<=z[5]-angel[5];
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[7]<=16'b0;
	y[7]<=16'b0;
	z[7]<=16'b0;
	end
	else
	begin
		if(z[6][15])
		begin
			x[7]<=$signed (x[6])-($signed (y[6])>>>7);
			y[7]<=$signed (y[6])-($signed (x[6])>>>7);
			z[7]<=z[6]+angel[6];
		end
		else
		begin
			x[7]<=$signed (x[6])+($signed (y[6])>>>7);
			y[7]<=$signed (y[6])+($signed (x[6])>>>7);
			z[7]<=z[6]-angel[6];
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[8]<=16'b0;
	y[8]<=16'b0;
	z[8]<=16'b0;
	end
	else
	begin
		if(z[7][15])
		begin
			x[8]<=$signed (x[7])-($signed (y[7])>>>8);
			y[8]<=$signed (y[7])-($signed (x[7])>>>8);
			z[8]<=z[7]+angel[7];
		end
		else
		begin
			x[8]<=$signed (x[7])+($signed (y[7])>>>8);
			y[8]<=$signed (y[7])+($signed (x[7])>>>8);
			z[8]<=z[7]-angel[7];
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[9]<=16'b0;
	y[9]<=16'b0;
	z[9]<=16'b0;
	end
	else
	begin
		if(z[8][15])
		begin
			x[9]<=$signed (x[8])-($signed (y[8])>>>9);
			y[9]<=$signed (y[8])-($signed (x[8])>>>9);
			z[9]<=z[8]+angel[8];
		end
		else
		begin
			x[9]<=$signed (x[8])+($signed (y[8])>>>9);
			y[9]<=$signed (y[8])+($signed (x[8])>>>9);
			z[9]<=z[8]-angel[8];
		end
	end
end

always@(posedge clk or negedge rst_n)
begin
	if(rst_n!=1)
	begin
	x[10]<=16'b0;
	y[10]<=16'b0;
	z[10]<=16'b0;
	end
	else
	begin
		if(z[9][15])
		begin
			x[10]<=$signed (x[9])-($signed (y[9])>>>10);
			y[10]<=$signed (y[9])-($signed (x[9])>>>10);
			z[10]<=z[9]+angel[9];
		end
		else
		begin
			x[10]<=$signed (x[9])+($signed (y[9])>>>10);
			y[10]<=$signed (y[9])+($signed (x[9])>>>10);
			z[10]<=z[9]-angel[9];
		end
	end
end
assign OutputData=($signed(x[10])+$signed(y[10]));
endmodule