仿照ZEDboard设计板子调试

最近,按照Zedboard设计了一个板子,看起来问题不大。但实际上开始上手就遇到问题。
首先是用了一个2百块的Xilinx USB cable, Vivado上直接报错,找不到server。后来借了一个原装的下载线,可以识别出server了,但是却找不到target,仔细排查了一遍,发现一个问题:
CFGBVS引脚拉低了,在没有写代码的情况下,Zynq的功耗就很大,几乎触手就会有点烫的感觉,而且输出引脚全部为高电平。后来CFGBVS引脚拉高后,功耗降低,其他引脚也都拉低了,但是直接接在引脚上的LED有点弱光。现在还么有找到具体的原因。

CFGBVS:
Configuration Banks Voltage Select CFGBVS determines the I/O voltage operating range and voltage tolerance for the dedicated configuration bank 0 and for the multi-function configuration pins in
banks 14 and 15 in the Spartan-7, Artix-7 and Kintex-7 families. CFGBVS selects the operating voltage for the dedicated bank 0 at all times in all 7 series devices.
CFGBVS selects the operating voltage for the multi-function configuration banks 14 and 15 only
during configuration.
Connect CFGBVS High or Low per the bank voltage requirements. If the VCCO_0 supply for bank 0 is supplied with 2.5V or 3.3V, then the CFGBVS pin must be tied High (i.e. connected to VCCO_0). Tie CFGBVS to Low (i.e. connected to GND), only if the VCCO_0 for bank 0 is less than or equal to 1.8V. If used during configuration, banks 14 and 15 should match the VCCO level applied to bank 0.

原因找到了,扩展FMC上的JATG口,使用了两个接口芯片,去掉后就能发现target了,而且工作正常了。
估计是这个两个接口芯片没使用对,拉高或拉低了某个jatg信号线。

做了5个板子,4个板子测试功能都正常了,但有1块板子的zynq直接烧坏了,测试发现1.0和1.8已经导通了,估计焊接师傅BGA没焊好,直接和其他电压短路,击穿了内核电压。

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