VHDL数字时钟设计

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity second is

port (clk,clr,en:in std_logic;

         sec0,sec1:out std_logic_vector(3 downto 0);

       co:outstd_logic);

end second;

architecture sec of second is

SIGNAL cnt1,cnt0:std_logic_vector(3 downto0);

begin

       process(clk)

       begin

       if(clk'eventand clk='1')then

              ifen='1' then

                     ifcnt1="0101" and cnt0="1001" then

                            co<='1';

                            cnt0<="0000";

                            cnt1<="0000";

                     elsifcnt0<"1001" then

                            cnt0<=(cnt0+1);

                     else

                         cnt0<="0000";

                            cnt1<=cnt1+1;

                            co<='0';

                     endif;

              endif;

       endif;

       min1<=cnt1;

       min0<=cnt0;

       endprocess;

end min;
---------------------