ZYNQ 学习之PLL产生时钟点亮LED

module pll_led(
    input clk_sys,
    input rst_n,
    output reg [7:0] led

    );
   wire       clk_50M;
   wire        locked;
    reg  [31:0] timer_cnt;
     
    
 //产生50MHz时钟给led工作使用   
    clk_wiz_0 clk_50M_init
       (
        // Clock out ports
        .clk_out1(clk_50M),     // output clk_out1
        // Status and control signals
        .reset(rst_n), // input reset
        .locked(locked),       // output locked
       // Clock in ports
        .clk_in1(clk_sys) 
        );      // input clk_in1
         
  always@(posedge clk_50M or negedge rst_n)  
  begin
    if(rst_n)
    begin
        led<=8'd0;
        timer_cnt<=32'd0;
    end
    else if (timer_cnt>=32'd49_999_999)   //1s对应的时钟计数
    begin
        led<=~led;
        timer_cnt<=32'd0;
     end
     else
     begin
         led<=led;
        timer_cnt<=timer_cnt+1'b1;
     end
end  
    
endmodule

这个例子比较简单，实验过程中注意复位引脚，rst_n是高电平有效还是低电平有效。