2-3 Verilog 7 段译码器（动态显示）

使用工具：Xilinx ISE 14.7

通过时间分频在4位7段数码管中显示2个数字，给人眼一个错觉是同时显示出两个数字。实现原理是轮流向各位数码管送出字形码和相应的位选信号，利用数码管闪烁的余晖和人眼视觉的暂留作用，使人感觉像各位管同时在显示，需要用到FPGA上的clock进行触发，代码如下：

module code(
	input wire [3:0] high_data,
	input wire [3:0] low_data,
	input wire clk,
	output reg [6:0] led,
	output reg [3:0] en
    );

reg [3:0] data;
reg [15:0] times;

initial times = 0;

always @ (posedge clk)
	begin
	times = times + 16'b1;
	if(times == 40000)
		times = 16'b0;
	end

always @ (posedge clk)
	begin
	if(times > 20000)
		begin
		en = 4'b1101;
		data = high_data;
		end
	else
		begin
		en = 4'b1110;
		data = low_data;
		end
    case(data)
        4'b0000: led = 7'b1000000;	//0
        4'b0001: led = 7'b1111001;	//1
        4'b0010: led = 7'b0100100;	//2
		  4'b0011: led = 7'b0110000;	//3
        4'b0100: led = 7'b0011001;	//4
        4'b0101: led = 7'b0010010;	//5
        4'b0110: led = 7'b0000010;	//6
        4'b0111: led = 7'b1111000;	//7
		  4'b1000: led = 7'b0000000;	//8
        4'b1001: led = 7'b0010000;	//9
        4'b1010: led = 7'b0001000;	//A
        4'b1011: led = 7'b0000011;	//b
        4'b1100: led = 7'b1000110;	//C
        4'b1101: led = 7'b0100001;	//d
        4'b1110: led = 7'b0000110;	//E
        4'b1111: led = 7'b0001110;	//F
    endcase
	end
endmodule

在这里使用“always @ (posedge clk)”表示每次始终上升沿到来时触发这一个always块，利用时钟分频的方法依次显示high_data与low_data两个数据

仿真时，时钟激励信号的产生语句：always#(period/2)clk = ~clk;

由于仿真结果比较难以解释，在这里就不列出来了，直接给出引脚文件与开发板实际效果图

NET "high_data[3]" LOC = "T5";
NET "high_data[2]" LOC = "V8";
NET "high_data[1]" LOC = "U8";
NET "high_data[0]" LOC = "N8";

NET "low_data[3]" LOC = "M8";
NET "low_data[2]" LOC = "V9";
NET "low_data[1]" LOC = "T9";
NET "low_data[0]" LOC = "T10";

NET "clk" LOC = "V10";

NET "en[3]" LOC = "P17";
NET "en[2]" LOC = "P18";
NET "en[1]" LOC = "N15";
NET "en[0]" LOC = "N16";

NET "led[6]" LOC = "L14";
NET "led[5]" LOC = "N14";
NET "led[4]" LOC = "M14";
NET "led[3]" LOC = "U18";
NET "led[2]" LOC = "U17";
NET "led[1]" LOC = "T18";
NET "led[0]" LOC = "T17";

效果图（高位输入4’b1010； 低位输入4’b0101）：