AXI_DMAC的寄存器说明

来自：https://wiki.analog.com/resources/fpga/docs/hdl/regmap#folded_1ef0a96bdee03491ff600d93e2c50767_1

这里是ADI提供的DMAC，不是XILINX的VIVADO自带的。请注意区分！

 

 

 

 

Address	Bits	Name	Type	Default	Description
DWORD
0x000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 4.02.61.
	[31:16]	VERSION_MAJOR	RO	0x04
	[15:8]	VERSION_MINOR	RO	0x02
	[7:0]	VERSION_PATCH	RO	0x61
0x001	PERIPHERAL_ID
	[31:0]	PERIPHERAL_ID	RO	ID	Value of the ID configuration parameter.
0x002	SCRATCH
	[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x003	IDENTIFICATION
	[31:0]	IDENTIFICATION	RO	0x444D4143	Peripheral identification ('D', 'M', 'A', 'C').
0x020	IRQ_MASK
	[1]	TRANSFER_COMPLETED	RW	0x1	Masks the TRANSFER_COMPLETED IRQ.
	[0]	TRANSFER_QUEUED	RW	0x1	Masks the TRANSFER_QUEUED IRQ.
0x021	IRQ_PENDING
	[1]	TRANSFER_COMPLETED	RW1C	0x0	This bit will be asserted if a transfer has been completed and the TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer.
	[0]	TRANSFER_QUEUED	RW1C	0x0	This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in theIRQ_MASK register.
0x022	IRQ_SOURCE
	[1]	TRANSFER_COMPLETED	RO	0x0	This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
	[0]	TRANSFER_QUEUED	RO	0x0	This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
0x100	CONTROL
	[1]	PAUSE	RW	0x0	When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again.
	[0]	ENABLE	RW	0x0	When set to 1 the DMA channel is enabled.
0x101	TRANSFER_ID
	[4:0]	TRANSFER_ID	RO	0x00	This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0.
0x102	TRANSFER_SUBMIT
	[0]	TRANSFER_SUBMIT	RW	0x00	Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMAchannel is disabled. Writing a 0 to this register has no effect.
0x103	FLAGS
	[0]	CYCLIC	RW	CYCLIC	Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated.
	[1]	TLAST	RW	0x1	When setting this bit for a MM to AXIS transfer the TLAST signal will be asserted during the last beat of the transfer. For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored. After its occurrence all descriptors are ignored until this bit is set.
	[2]	PARTIAL_REPORTING_EN	RW	0x0	When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
	[3]	FRAME_LOCK_EN	RW	0x0	When setting this bit the module will operate in frame lock mode.
0x104	DEST_ADDRESS
	[31:0]	DEST_ADDRESS	RW	0x00000000	This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support.
0x105	SRC_ADDRESS
	[31:0]	SRC_ADDRESS	RW	0x00000000	This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support.
0x106	X_LENGTH
	[23:0]	X_LENGTH	RW	{log2(max(	Number of bytes to transfer - 1.
				DMA_DATA_WIDTH_SRC,
				DMA_DATA_WIDTH_DEST
				)/8){1'b1}}
0x107	Y_LENGTH
	[23:0]	Y_LENGTH	RW	0x000000	Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
0x108	DEST_STRIDE
	[23:0]	DEST_STRIDE	RW	0x000000	The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMAchannel has been configured with 2D transfer support and write to memory support.
0x109	SRC_STRIDE
	[23:0]	SRC_STRIDE	RW	0x000000	The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMAchannel has been configured with 2D transfer and read from memory support.
0x10a	TRANSFER_DONE				If bit x is set in this register the transfer with ID x has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
	[0]	TRANSFER_0_DONE	RO	0x0	If this bit is set the transfer with ID 0 has been completed.
	[1]	TRANSFER_1_DONE	RO	0x0	If this bit is set the transfer with ID 1 has been completed.
	[2]	TRANSFER_2_DONE	RO	0x0	If this bit is set the transfer with ID 2 has been completed.
	[3]	TRANSFER_3_DONE	RO	0x0	If this bit is set the transfer with ID 3 has been completed.
	[31]	PARTIAL_TRANSFER_DONE	RO	0x0	If this bit is set at least one partial transfer was transferred. This field will reset when the ENABLE control bit is reset or when all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and PARTIAL_TRANSFER_ID registers.
0x10b	ACTIVE_TRANSFER_ID
	[4:0]	ACTIVE_TRANSFER_ID	RO	0x00	ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register.
0x10c	STATUS
	[31:0]	RESERVED	RO	0x00	This register is reserved for future usage. Reading it will always return 0.
0x10d	CURRENT_DEST_ADDRESS
	[31:0]	CURRENT_DEST_ADDRESS	RO	0x00	Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support.
0x10e	CURRENT_SRC_ADDRESS
	[31:0]	CURRENT_SRC_ADDRESS	RO	0x00	Address form which the next data sample is read. This register is only valid if the DMAchannel has been configured for read from memory support.
0x112	TRANSFER_PROGRESS
	[23:0]	TRANSFER_PROGRESS	RO	0x000000	This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only.
0x113	PARTIAL_TRANSFER_LENGTH
	[31:0]	PARTIAL_LENGTH	RO	0x000000	Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers.
0x114	PARTIAL_TRANSFER_ID				Must be read after the PARTIAL_TRANSFER_LENGTH registers.
	[1:0]	PARTIAL_TRANSFER_ID	RO	0x0	ID of the transfer that was partial.
0x115	FRAME_LOCK_CONFIG
	[5:0]	FLOCK_NUMFRAMES	RW	0x00	Number of frame buffers to cycle through. Valid range 1..MAX_NUM_FRAMES synthesis parameter.
	[8]	FLOCK_MODE	RW	0x0	0 - Dynamic mode. In this mode the writer DMA (s2mm) will not step on the currently read buffer. In this mode the reader DMA(mm2s) will always read the most recent complete buffer. To be used in any-to-any frame rate adaptation applications. 1 - Simple mode. In this mode the writer will cycle through MAX_NUM_FRAMES buffers without caring about the reader. The reader will stay behind the writer with a predefined number of buffers described by FLOCK_FRAMEDISTANCE field. To be used in applications with similar read-write frame rate, to induce a programmed frame delay between writer and reader.
	[9]	FLOCK_WAIT_WRITER	RW	0x0	This field is valid only if the core is configured in reader mode (mm2s configuration). 0 - In this mode, once the core is enabled the reader will start to access a buffer immediately without the writer filled it first, resulting in outputting random data. 1 - In this mode, once the core is enabled the reader will wait the master to fill FLOCK_FRAMEDISTANCE+1 buffers before starting to read it. This ensures a smooth start without reading invalid data from the buffers. During the wait period external synchronization requests are ignored.
	[20:16]	FLOCK_FRAMEDISTANCE	RW	0x00	Number of frames the reader DMA (mm2s) will stay behind the writer DMA minus one. Valid only when DMAC is in reader mode, it is in simple flock mode (FLOCK_MODE is 1) and FRAME_LOCK_EN bit from FLAGS register is set. Valid range 0..FLOCK_NUMFRAMES-2 e.g 0 - Reader will operate on the latest available buffer.; FLOCK_NUMFRAMES-2 - Reader will operate on the oldest available buffer.
0x116	FRAME_LOCK_STRIDE
	[31:0]	FLOCK_FRAMESTRIDE	RW	0x00	Stride of consecutive frames in memory in bytes. Should be at least the size of one frame (X_LENGTH+1) * (Y_LENGTH+1);