SystemVerilog软约束

普通约束称为硬约束，因为求解器必须始终满足它们。 如果求解器找不到解决方案，则随机化将失败。

但是，声明为软约束可以使求解器具有一定的灵活性，如果存在其他相互矛盾的约束（硬约束或优先级较高的软约束），则需要满足该约束。

软约束用于为随机变量指定默认值和分布。

例

在下面的示例中显示了一个软约束，该约束告诉求解器为名为data的变量生成4到12之间的值。

class ABC;
  rand bit [3:0] data;
 
  // This constraint is defined as "soft" 
  constraint c_data { soft data >= 4;
                     data <= 12; }
endclass
 
module tb;
  ABC abc;
 
  initial begin
    abc = new;
    for (int i = 0; i < 5; i++) begin
      abc.randomize();
      $display ("abc = 0x%0h", abc.data);
    end
  end
endmodule

Simulation Log
ncsim> run
abc = 0x4
abc = 0x8
abc = 0x4
abc = 0x7
abc = 0x7
ncsim: *W,RNQUIE: Simulation is complete.

让我们看看在这种情况下如何处理矛盾的内联约束。

module tb;
  ABC abc;
 
  initial begin
    abc = new;
    for (int i = 0; i < 5; i++) begin
      abc.randomize() with { data == 2; };
      $display ("abc = 0x%0h", abc.data);
    end
  end
endmodule

Simulation Log
ncsim> run
abc = 0x2
abc = 0x2
abc = 0x2
abc = 0x2
abc = 0x2
ncsim: *W,RNQUIE: Simulation is complete.

看到矛盾的内联约束允许求解程序将变量的值约束为2。请记住，这是矛盾的，因为原始约束c数据应该将其约束在4和12之内，但是内联约束要求将变量设置为2，这超出了原始范围。

Simulation Log
ncsim> run
abc = 0x2
abc = 0x2
abc = 0x2
abc = 0x2
abc = 0x2
ncsim: *W,RNQUIE: Simulation is complete.

它与硬约束有何不同？

让我们采用ABC类，通过删除soft关键字将其变成硬约束，并应用一个相互矛盾的内联约束。

class ABC;
  rand bit [3:0] data;
 
  constraint c_data { data >= 4;
                     data <= 12; }
endclass
 
module tb;
  ABC abc;
 
  initial begin
    abc = new;
    for (int i = 0; i < 1; i++) begin
      abc.randomize() with { data == 2; };
      $display ("abc = 0x%0h", abc.data);
    end
  end
endmodule

Simulation Log
ncsim> run
      abc.randomize() with { data == 2; };
                  |
ncsim: *W,SVRNDF (./testbench.sv,14|18): The randomize method call failed. The unique id of the failed randomize call is 4.
Observed simulation time : 0 FS + 0
ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:

  constraint c_data { data >= 4; (./testbench.sv,4)
      abc.randomize() with { data == 2; }; (./testbench.sv,14)
ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:

rand variables:
       data [./testbench.sv, 2]

abc = 0x0
ncsim: *W,RNQUIE: Simulation is complete.

在这种情况下，求解器由于约束矛盾而失败，因此将变量数据分配为0。
参考文献：
【1】https://www.chipverify.com/systemverilog/systemverilog-soft-constraints