数字IC笔试题|verilog实现N(1-8)分频的时钟分频器，占空比50%

题目如下：

Verilog实现如下：

module divider(clk ,rst_n ,divider_num ,clk_out);
   input clk,rst_n;
   input [3:0] divider_num;
   output clk_out;
    
    reg [7:0] divider_en;
    
    always@(*)
    begin
    if(rst_n==1'b0)
          divider_en=8'b0000_0000;
    else 
         begin 
           case(divider_num) 
                 4'b0001 :  divider_en<=8'b0000_0001;  // 1 奇数
                 4'b0010 :  divider_en<=8'b0000_0010;  // 2 偶数
                 4'b0011 :  divider_en<=8'b0000_0100;  // 3 奇数
                 4'b0100 :  divider_en<=8'b0000_1000; //  4 偶数
                 4'b0101 :  divider_en<=8'b0001_0000; //  5 奇数
                 4'b0110 :  divider_en<=8'b0010_0000; //  6 偶数
                 4'b0111 :  divider_en<=8'b0100_0000; //  7 奇数
                 4'b1000 :  divider_en<=8'b1000_0000;  // 8 偶数 
                 default:  divider_en<=8'b0000_0000;
            endcase
         end 
    end 
    
    reg [2:0] cnt  ;
    always@(posedge clk or negedge rst_n)
    begin 
    if(rst_n==1'b0)
         cnt<=3'd0;
    else
      begin  
          if(cnt==(divider_num-1'd1))
            cnt<=3'd0;
          else
            cnt<=cnt+1'd1;
       end 
    end 
    
    reg clk_out_temp;
    
    always@(posedge clk or negedge rst_n)
    begin 
    if(rst_n==1'b0)
        clk_out_temp<=1'b0;
    else  
      begin 
       case(divider_en) 
          8'b0000_0000: clk_out_temp<=1'b0;
          8'b0000_0001: clk_out_temp<=1'b0;                     //1
          8'b0000_0010: begin               //2
                              if(cnt==3'd0)
                                  clk_out_temp<=1'b1;
                              else 
                                  clk_out_temp<=1'b0;
                         end
          8'b0000_0100:  begin              //3
                              if(cnt==3'd0 || cnt==3'd1 )
                                 clk_out_temp<=~clk_out_temp;
                              else 
                                 clk_out_temp<=clk_out_temp;
                         end
          8'b0000_1000,8'b0001_0000: begin  //4、5
                               if(cnt==3'd0 || cnt==3'd2)
                                   clk_out_temp<=~clk_out_temp;
                               else 
                                   clk_out_temp<=clk_out_temp;
                               end 
          8'b0010_0000,8'b0100_0000: begin   //6、7
                               if(cnt==3'd0 || cnt==3'd3)
                                    clk_out_temp<=~clk_out_temp;
                               else 
                                    clk_out_temp<=clk_out_temp;
                               end 
          8'b1000_0000: begin
                               if(cnt==3'd0 || cnt==3'd4)
                                    clk_out_temp<=~clk_out_temp;
                               else 
                                    clk_out_temp<=clk_out_temp;
                               end 
       endcase
     end
    end
    
    reg clk_out_temp1;
    always@(negedge clk or negedge rst_n)
    begin 
    if(rst_n==1'b0)
         clk_out_temp1<=1'b0;
    else if(divider_en[2] || divider_en[4] || divider_en[6])
         clk_out_temp1<=clk_out_temp;
    end 
    
    assign clk_out=divider_en[0]? clk:((divider_en[2] || divider_en[4] || divider_en[6]) ? (clk_out_temp1|clk_out_temp):(clk_out_temp)); 
                          
       
    
   
   
 
endmodule 

testbench:

module divider_tb;
        reg     clk ;
        reg rst_n ;
        reg [3:0] divider_num ;
        wire clk_out;
        
        parameter N=20;
        
        initial clk=1'b0;
        always#(N/2)clk = ~clk;
        
        initial 
               begin
                  rst_n=1'b0;
                  divider_num=4'd0;
                  #(100*N)
                  rst_n=1'b1;divider_num=4'd1;
                  #(100*N) 
                  divider_num=4'd2;
                  #(100*N) 
                  divider_num=4'd3; 
                  #(100*N) 
                  divider_num=4'd4;
                  #(100*N)
                  divider_num=4'd5; 
                  #(100*N) 
                  divider_num=4'd6;
                  #(100*N) 
                  divider_num=4'd7;
                  #(100*N) 
                  divider_num=4'd8;
                  #(100*N) $stop;         
                end
       
      
        divider divider(
           .clk(clk) ,
           .rst_n(rst_n) ,
            .divider_num(divider_num) ,
           .clk_out(clk_out)
        );

endmodule 

仿真结果：