FPGA 练习demo

demo1:FPGA驱动LED静态显示

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (seg:in std_logic_vector(3 downto 0 );   --四位二进制码输入
q3:out std_logic_vector(6 downto 0) );   --输出LED七段码
end decoder;

architecture Behavioral of decoder is
begin
process(seg)
begin
case seg is
when "0000" => q3<="0000001";--0   
when "0001" => q3<="1001111";--1
when "0010" => q3<="0010010";--2
when "0011" => q3<="0000110";--3
when "0100" => q3<="1001100" --4
when "0101" => q3<="0100100";--5
when "0110" => q3<="0100000";--6
when "0111" => q3<="0001111";--7
when "1000" => q3<="0000000";--8
when "1001" => q3<="0000100";--9
when others => q3<="1111111";
end case;
end process;
end Behavioral;

led 动态显示：
 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dynamic is	
  Port ( clk : in std_logic;
	   reset: in std_logic;
	 din1 : in std_logic_vector(6 downto 0);       --译码后的数据信号1（4位2进制数据
通过例1中的decoder模块译码得到din1,din2,din3,din4）
       din2 : in std_logic_vector(6 downto 0);       --译码后的数据信号2
       din3 : in std_logic_vector(6 downto 0);       --译码后的数据信号3
       din4 : in std_logic_vector(6 downto 0);       --译码后的数据信号4
	   shift: out std_logic_vector(3 downto 0);      --位选信号
       bus4 : out std_logic_vector(6 downto 0));     --数据信号
end dynamic;

architecture Behavioral of dynamic is
  signal scan_clk:std_logic_vector(1 downto 0);
begin
process(clk,scan_clk,reset)                        --分频进程
variable scan:std_logic_vector(17 downto 0);
begin
if reset='1' then
scan:="000000000000000000";
	scan_clk<="00";
elsif clk'event and clk='1'then
scan:=scan+1;
end if;
	scan_clk<=scan(17 downto 16);
end process;

process(scan_clk,din1,din2,din3,din4)       --扫描进程
begin
case scan_clk is
when "00"=>
	  bus4<=din1;
	  shift<="0001";
	when "01"=>
	  bus4<=din2;
	  shift<="0010";
	when "10"=>
	  bus4<=din3;
	  shift<="0100";
when "11"=>
	  bus4<=din4;
	  shift<="1000";
	when others=> bus4<="0000000";shift<="0000";
end case;
end process;  

end Behavioral;

本地文件位置：F:\FPGA_project