一、部件介绍
PLL(锁相环)：时钟信号通常由晶振提供，但面对多变的时钟需求，无法定制晶振，因此可以利用锁相环将晶振时钟信号进行放大，并且数值可通过参数确定。
DIV(分频器)：PLL数量有限，但每个部件的时钟频率相差较大，故通过分配器，将高频时钟降下来，供相应部件使用。
MUX(复用器)：每个部件可以通过MUX，选择时钟来源。
二、初始化步骤
1、设置PLL锁定时间，在此期间保证程序能正常执行。
2、设置PLL输出频率，通过配置寄存器，让PLL输出指定的时钟。
3、设置DIV分频参数
4、等待PLL稳定，只有PLL稳定了，才能配置MUX。
5、配置MUX，为每个部件选择合适的时钟源。
三、配置步骤
在clock_init_exynos4412.c中进行时钟初始化，其函数如下所示
void system_clock_init(void)
{
struct exynos4x12_clock volatile *clk = (struct exynos4x12_clock volatile *)samsung_get_base_clock();
/**
* Setup 1:
* 配置锁相环(PLL)
*
*/
/* Set PLL locktime */
writel(PLL_LOCKTIME, &clk->apll_lock);
writel(PLL_LOCKTIME, &clk->mpll_lock);
writel(PLL_LOCKTIME, &clk->epll_lock);
writel(PLL_LOCKTIME, &clk->vpll_lock);
/*配置锁相环，让其输出指定频率的时钟信号*/
writel(APLL_CON0_VAL, &clk->apll_con0);
writel(APLL_CON1_VAL, &clk->apll_con1);
writel(MPLL_CON0_VAL, &clk->mpll_con0);
writel(MPLL_CON1_VAL, &clk->mpll_con1);
writel(EPLL_CON0_VAL, &clk->epll_con0);
writel(EPLL_CON1_VAL, &clk->epll_con1);
writel(VPLL_CON0_VAL, &clk->vpll_con0);
writel(VPLL_CON1_VAL, &clk->vpll_con1);
/**
* Setup 2：
* 锁相环时钟状态切环需要时间，不选择等待，直接配置分频率器
*/
writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
writel(CLK_DIV_TOP_VAL, &clk->div_top);
writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
writel(CLK_DIV_CAM_VAL, &clk->div_cam);
writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
writel(CLK_DIV_LCD_VAL, &clk->div_lcd);
/**
* Setup 3:
* 确认锁相环工作正常，才能切换通路
*/
while(!(clk->apll_con0 & (1 << 29)));
while(!(clk->mpll_con0 & (1 << 29)));
while(!(clk->epll_con0 & (1 << 29)));
while(!(clk->vpll_con0 & (1 << 29)));
/**
* Setup 4:
* 配置多路复用器，选择合适的时钟通路
*/
writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
writel(CLK_SRC_CAM_VAL, &clk->src_cam);
writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
writel(CLK_SRC_LCD_VAL, &clk->src_lcd);
sdelay(0x1000);
}
四、配置参数
配置参数位于exynos4412_setup.h,如下所示
/**
* 选择时钟
*/
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif
/********************************************************************************
*
* 配置时钟信息
*
********************************************************************************/
/**
* 锁相环的配置信息
*/
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME 0x920
/* PLL Values */
#define DISABLE 0
#define ENABLE 1
#define SET_PLL(pdiv, mdiv, sdiv) ((sdiv << 0) \
| (pdiv << 8) \
| (mdiv << 16) \
| (ENABLE << 31))
/* APLL_CON0 1GHz */
#define APLL_PDIV 0x3
#define APLL_MDIV 0x7D
#define APLL_SDIV 0x0
#define APLL_CON0_VAL SET_PLL(APLL_PDIV, APLL_MDIV, APLL_SDIV)
/* APLL_CON1 */
#define APLL_AFC_ENB 0x1
#define APLL_AFC 0xC
#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
/* MPLL_CON0 800Hz*/
#define MPLL_PDIV 0x3
#define MPLL_MDIV 0x64
#define MPLL_SDIV 0x0
#define MPLL_CON0_VAL SET_PLL(MPLL_PDIV, MPLL_MDIV, MPLL_SDIV)
/* MPLL_CON1 */
#define MPLL_AFC_ENB 0x0
#define MPLL_AFC 0x1C
#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
/* EPLL_CON0 400Hz*/
#define EPLL_PDIV 0x3
#define EPLL_MDIV 0x64
#define EPLL_SDIV 0x1
#define EPLL_CON0_VAL SET_PLL(EPLL_PDIV, EPLL_MDIV, EPLL_SDIV)
/* EPLL_CON1 */
#define EPLL_K 0x0
#define EPLL_CON1_VAL (EPLL_K << 0)
/* VPLL_CON0 100Hz*/
#define VPLL_PDIV 0x3
#define VPLL_MDIV 0x64
#define VPLL_SDIV 0x3
#define VPLL_CON0_VAL SET_PLL(VPLL_PDIV, VPLL_MDIV, VPLL_SDIV)
/* VPLL_CON1 */
#define VPLL_K 0x0
#define VPLL_SSCG_EN DISABLE
#define VPLL_SEL_PF_DN_SPREAD 0x0
#define VPLL_MRR 0x11
#define VPLL_MFR 0x0
#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
| (VPLL_SEL_PF_DN_SPREAD << 29) \
| (VPLL_MRR << 24) \
| (VPLL_MFR << 16) \
| (VPLL_K << 0))
/**
* 配置多路复用器MUX，分频器DIV
*/
/* CLK_SRC_CPU */
#define MUX_APLL_SEL_FILPLL 0x0
#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
#define MUX_CORE_SEL_MOUTAPLL 0x0
#define MUX_CORE_SEL_SCLKMPLL 0x1
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
#define MUX_MPLL_SEL_FILPLL 0x0
#define MUX_MPLL_SEL_FOUTMPLL 0x1
#define CLK_SRC_CPU_VAL ((MUX_APLL_SEL_MOUTMPLLFOUT << 0) \
| (MUX_CORE_SEL_MOUTAPLL << 16) \
| (MUX_HPM_SEL_MOUTAPLL << 20) \
| (MUX_MPLL_SEL_FOUTMPLL << 24))
/* CLK_DIV_CPU0 */
#define CORE_RATIO 0x0
#define COREM0_RATIO 0x3
#define COREM1_RATIO 0x7
#define PERIPH_RATIO 0x3
#define ATB_RATIO 0x4
#define PCLK_DBG_RATIO 0x1
#define APLL_RATIO 0x1
#define CORE2_RATIO 0x0
#define CLK_DIV_CPU0_VAL ((CORE_RATIO << 0) \
| (COREM0_RATIO << 4) \
| (COREM1_RATIO << 8) \
| (PERIPH_RATIO << 12) \
| (ATB_RATIO << 16) \
| (PCLK_DBG_RATIO << 20) \
| (APLL_RATIO << 24) \
| (CORE2_RATIO << 28))
/* CLK_DIV_CPU1 */
#define COPY_RATIO 0x4
#define HPM_RATIO 0x0
#define CORES_RATIO 0x0
#define CLK_DIV_CPU1_VAL ((COPY_RATIO) | (HPM_RATIO << 4) | (CORES_RATIO << 8))
/* CLK_SRC_DMC */
#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
#define MUX_DPHY_SEL_SCLKMPLL 0x0
#define MUX_DPHY_SEL_SCLKAPLL 0x1
#define MUX_MPLL_SEL_FINPLL 0x0
#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
#define MUX_PWI_SEL_XXTI 0x0
#define MUX_PWI_SEL_XUSBXTI 0x1
#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
#define MUX_PWI_SEL_SCLKMPLL 0x6
#define MUX_PWI_SEL_SCLKEPLL 0x7
#define MUX_PWI_SEL_SCLKVPLL 0x8
#define MUX_G2D_ACP_0_SEL_SCLKMPL 0x0
#define MUX_G2D_ACP_0_SEL_SCLKAPLL 0x1
#define MUX_G2D_ACP_1_SEL_SCLKEPLL 0x0
#define MUX_G2D_ACP_1_SEL_SCLKVPLL 0x1
#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_0 0x0
#define MUX_G2D_ACP_SEL_MOUTG2D_ACP_1 0x1
#define CLK_SRC_DMC_VAL ((MUX_DMC_BUS_SEL_SCLKMPLL << 4) \
| (MUX_DPHY_SEL_SCLKMPLL << 8) \
| (MUX_MPLL_SEL_MOUTMPLLFOUT << 12) \
| (MUX_PWI_SEL_XUSBXTI << 16) \
| (MUX_G2D_ACP_0_SEL_SCLKMPL << 20) \
| (MUX_G2D_ACP_1_SEL_SCLKEPLL << 24) \
| (MUX_G2D_ACP_SEL_MOUTG2D_ACP_0 << 28))
/* CLK_DIV_DMC0 */
#define ACP_RATIO 0x3
#define ACP_PCLK_RATIO 0x1
#define DPHY_RATIO 0x1
#define DMC_RATIO 0x1
#define DMCD_RATIO 0x1
#define DMCP_RATIO 0x1
#define CLK_DIV_DMC0_VAL ((ACP_RATIO << 0) \
| (ACP_PCLK_RATIO << 4) \
| (DPHY_RATIO << 8) \
| (DMC_RATIO << 12) \
| (DMCD_RATIO << 16) \
| (DMCP_RATIO << 20))
/* CLK_DIV_DMC1 */
#define G2D_ACP_RATIO 0x3
#define C2C_RATIO 0x1
#define PWI_RATIO 0x1
#define C2C_ACLK_RATIO 0x1
#define DVSEM_RATIO 0x1
#define DPM_RATIO 0x1
#define CLK_DIV_DMC1_VAL ((G2D_ACP_RATIO << 0) \
| (C2C_RATIO << 4) \
| (PWI_RATIO << 8) \
| (C2C_ACLK_RATIO << 12) \
| (DVSEM_RATIO << 16) \
| (DPM_RATIO << 24))
/* CLK_SRC_TOP0 */
#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
#define MUX_EPLL_SEL_FINPLL 0x0
#define MUX_EPLL_SEL_FOUTEPLL 0x1
#define MUX_VPLL_SEL_FINPLL 0x0
#define MUX_VPLL_SEL_FOUTVPLL 0x1
#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
#define MUX_ONENAND_SEL_ACLK_133 0x0
#define MUX_ONENAND_SEL_ACLK_160 0x1
#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_1_SEL_MOUTONENAND << 0) \
| (MUX_EPLL_SEL_FOUTEPLL << 4) \
| (MUX_VPLL_SEL_FOUTVPLL << 8) \
| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
| (MUX_ACLK_133_SEL_SCLKAPLL << 24)\
| (MUX_ONENAND_SEL_ACLK_133 << 28))
/* CLK_SRC_TOP1 */
#define MUX_ACLK_266_GPS_SEL_SCLKMPLL 0x0
#define MUX_ACLK_266_GPS_SEL_SCLKAPL 0x1
#define MUX_ACLK_400_MCUISP_SEL_SCLKMPLL 0x0
#define MUX_ACLK_400_MCUISP_SEL_SCLKAPLL 0x1
#define MUX_MPLL_USER_SEL_T_FINPLL 0x0
#define MUX_MPLL_USER_SEL_T_SCLKMPLLL 0x1
#define MUX_ACLK_266_GPS_SUB_SEL_FINPLL 0x0
#define MUX_ACLK_266_GPS_SUB_SEL_DIVOUT 0x1
#define MUX_ACLK_200_SUB_SEL_FINPL 0x0
#define MUX_ACLK_200_SUB_SEL_DIVOUT 0x1
#define MUX_ACLK_400_MCUISP_SUB_SEL_FINPLL 0x0
#define MUX_ACLK_400_MCUISP_SUB_SEL_DIVOUT 0x1
#define CLK_SRC_TOP1_VAL ((MUX_ACLK_266_GPS_SEL_SCLKMPLL << 4) \
| (MUX_ACLK_400_MCUISP_SEL_SCLKMPLL << 8) \
| (MUX_MPLL_USER_SEL_T_SCLKMPLLL << 12) \
| (MUX_ACLK_266_GPS_SUB_SEL_DIVOUT << 16) \
| (MUX_ACLK_200_SUB_SEL_DIVOUT << 20) \
| (MUX_ACLK_400_MCUISP_SUB_SEL_DIVOUT << 24))
/* CLK_DIV_TOP */
#define ACLK_200_RATIO 0x3
#define ACLK_100_RATIO 0x7
#define ACLK_160_RATIO 0x4
#define ACLK_133_RATIO 0x5
#define ONENAND_RATIO 0x0
#define ACLK_266_GPS_RATIO 0x2
#define ACLK_400_MCUISP_RATIO 0x1
#define CLK_DIV_TOP_VAL ((ACLK_200_RATIO << 0) \
| (ACLK_100_RATIO << 4)\
| (ACLK_160_RATIO << 8) \
| (ACLK_133_RATIO << 12) \
| (ONENAND_RATIO << 16) \
| (ACLK_266_GPS_RATIO << 20) \
| (ACLK_400_MCUISP_RATIO << 24))
/* CLK_SRC_LEFTBUS */
#define MUX_GDL_SEL_SCLKMPLL 0x0
#define MUX_GDL_SEL_SCLKAPLL 0x1
#define MUX_MPLL_USER_SEL_L_FINPLL 0x0
#define MUX_MPLL_USER_SEL_L_FOUTMPLL 0x1
#define CLK_SRC_LEFTBUS_VAL ((MUX_GDL_SEL_SCLKMPLL) | (MUX_MPLL_USER_SEL_L_FOUTMPLL << 4))
/* CLK_DIV_LEFTBUS */
#define GDL_RATIO 0x3
#define GPL_RATIO 0x1
#define CLK_DIV_LEFTBUS_VAL ((GDL_RATIO) | (GPL_RATIO << 4))
/* CLK_SRC_RIGHTBUS */
#define MUX_GDR_SEL_SCLKMPLL 0x0
#define MUX_GDR_SEL_SCLKAPLL 0x1
#define MUX_MPLL_USER_SEL_R_FINPLL 0x0
#define MUX_MPLL_USER_SEL_R_FOUTMPLL 0x1
#define CLK_SRC_RIGHTBUS_VAL ((MUX_GDR_SEL_SCLKMPLL) | (MUX_MPLL_USER_SEL_R_FOUTMPLL << 4))
/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO 0x1
#define GDR_RATIO 0x3
#define CLK_DIV_RIGHTBUS_VAL ((GDR_RATIO) | (GPR_RATIO << 4))
/* CLK_SRC_PERIL0 */
#define UART_SEL_XXTI 0
#define UART_SEL_XUSBXTI 1
#define UART_SEL_SCLK_HDMI24M 2
#define UART_SEL_SCLK_USBPHY0 3
#define UART_SEL_SCLK_USBPHY1 4
#define UART_SEL_SCLK_HDMIPHY 5
#define UART_SEL_SCLKMPLL 6
#define UART_SEL_SCLKEPLL 7
#define UART_SEL_SCLKVPLL 8
#define UART0_SEL UART_SEL_SCLKMPLL
#define UART1_SEL UART_SEL_SCLKMPLL
#define UART2_SEL UART_SEL_SCLKMPLL
#define UART3_SEL UART_SEL_SCLKMPLL
#define UART4_SEL UART_SEL_SCLKMPLL
#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL << 0))
/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
/* CLK_DIV_PERIL0 */
#define UART0_RATIO 7
#define UART1_RATIO 7
#define UART2_RATIO 7
#define UART3_RATIO 7
#define UART4_RATIO 7
#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
| (UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO << 0))
/* CLK_SRS_FSYS: 6 = SCLKMPLL */
#define SATA_SEL_SCLKMPLL 0
#define SATA_SEL_SCLKAPLL 1
#define MMC_SEL_XXTI 0
#define MMC_SEL_XUSBXTI 1
#define MMC_SEL_SCLK_HDMI24M 2
#define MMC_SEL_SCLK_USBPHY0 3
#define MMC_SEL_SCLK_USBPHY1 4
#define MMC_SEL_SCLK_HDMIPHY 5
#define MMC_SEL_SCLKMPLL 6
#define MMC_SEL_SCLKEPLL 7
#define MMC_SEL_SCLKVPLL 8
#define MMCC0_SEL MMC_SEL_SCLKMPLL
#define MMCC1_SEL MMC_SEL_SCLKMPLL
#define MMCC2_SEL MMC_SEL_SCLKMPLL
#define MMCC3_SEL MMC_SEL_SCLKMPLL
#define MMCC4_SEL MMC_SEL_SCLKMPLL
#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
| (MMCC4_SEL << 16) \
| (MMCC3_SEL << 12) \
| (MMCC2_SEL << 8) \
| (MMCC1_SEL << 4) \
| (MMCC0_SEL << 0))
/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
/* CLK_DIV_FSYS1 */
#define MMC0_RATIO 0xF
#define MMC0_PRE_RATIO 0x0
#define MMC1_RATIO 0xF
#define MMC1_PRE_RATIO 0x0
#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
| (MMC1_RATIO << 16) \
| (MMC0_PRE_RATIO << 8) \
| (MMC0_RATIO << 0))
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO 0xF
#define MMC2_PRE_RATIO 0x0
#define MMC3_RATIO 0xF
#define MMC3_PRE_RATIO 0x0
#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
| (MMC3_RATIO << 16) \
| (MMC2_PRE_RATIO << 8) \
| (MMC2_RATIO << 0))
/* CLK_DIV_FSYS3 */
#define MMC4_RATIO 0xF
#define MMC4_PRE_RATIO 0x0
#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
| (MMC4_RATIO << 0))
/* Clock Source CAM/FIMC */
/* CLK_SRC_CAM */
#define CAM0_SEL_XUSBXTI 1
#define CAM1_SEL_XUSBXTI 1
#define CSIS0_SEL_XUSBXTI 1
#define CSIS1_SEL_XUSBXTI 1
#define FIMC_SEL_SCLKMPLL 6
#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
| (CSIS0_SEL_XUSBXTI << 24) \
| (CAM1_SEL_XUSBXTI << 20) \
| (CAM0_SEL_XUSBXTI << 16) \
| (FIMC3_LCLK_SEL << 12) \
| (FIMC2_LCLK_SEL << 8) \
| (FIMC1_LCLK_SEL << 4) \
| (FIMC0_LCLK_SEL << 0))
/* SCLK CAM */
/* CLK_DIV_CAM */
#define FIMC0_LCLK_RATIO 4
#define FIMC1_LCLK_RATIO 4
#define FIMC2_LCLK_RATIO 4
#define FIMC3_LCLK_RATIO 4
#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
| (FIMC2_LCLK_RATIO << 8) \
| (FIMC1_LCLK_RATIO << 4) \
| (FIMC0_LCLK_RATIO << 0))
/* SCLK MFC */
/* CLK_SRC_MFC */
#define MFC_SEL_MPLL 0
#define MOUTMFC_0 0
#define MFC_SEL MOUTMFC_0
#define MFC_0_SEL MFC_SEL_MPLL
#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
/* CLK_DIV_MFC */
#define MFC_RATIO 3
#define CLK_DIV_MFC_VAL (MFC_RATIO)
/* SCLK G3D */
/* CLK_SRC_G3D */
#define G3D_SEL_MPLL 0
#define MOUTG3D_0 0
#define G3D_SEL MOUTG3D_0
#define G3D_0_SEL G3D_SEL_MPLL
#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL))
/* CLK_DIV_G3D */
#define G3D_RATIO 1
#define CLK_DIV_G3D_VAL (G3D_RATIO)
/* SCLK LCD */
/* CLK_SRC_LCD */
#define FIMD_SEL_SCLKMPLL 6
#define MDNIE0_SEL_XUSBXTI 1
#define MDNIE_PWM0_SEL_XUSBXTI 1
#define MIPI0_SEL_XUSBXTI 1
#define CLK_SRC_LCD_VAL ((MIPI0_SEL_XUSBXTI << 12) \
| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
| (MDNIE0_SEL_XUSBXTI << 4) \
| (FIMD_SEL_SCLKMPLL << 0))
/* CLK_DIV_LCD */
#define FIMD0_RATIO 4
#define CLK_DIV_LCD_VAL (FIMD0_RATIO)
五、图解时钟
CMU_CPU.png
CMU_DMC.png
CMU_TOP.png
CMU_BUS.png
六 验证配置
修改函数 do_lowlevel_init，烧写运行，发现灯闪烁频率快许多，说明时钟配置成功。
217 lamp(0, 2, 30, 0x8FFFFF);
218
219 if (actions & DO_CLOCKS) {
220 system_clock_init();
221
222 lamp(0, 2, 3000, 0x8FFFFF);