Circuits--Sequential Logic--Finite State Machines--Fsm2

网址:https://hdlbits.01xz.net/wiki/Fsm2

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @

你可能感兴趣的:(HDLbits,fpga,verilog)