UVM TLM之analysis_port的write函数

analysis端口

• analysis_port/analysis_export(analysis_imp) 没有阻塞和非阻塞概念
• 在analysis_imp所在的模块必须定义一个 write函数；
• write函数收到的数据放到run_phase中处理需要存放到队列中并借助一个event；(example)

具体过程:

1. analysis_port的write函数会依次获取与其相连的analysis_imp,并调用analysis_imp的write函数;

reference: src/tlm1/uvm_analysis_port.svh

2. 在analysis_imp的函数内部,会调用analysis_imp所在uvm_component的write函数,所以analysis_imp所在的uvm_component中一定要有一个write函数实现.

但是,需要注意的是,如果analysis_imp采用的是`uvm_analysis_imp_decl(*),就不需要uvm_analysis_imp_*所在的uvm_component中有write函数,而是要有write_*函数.(参考/uvm-1.2/macros/uvm_tlm_defines.svh)

关键点就在于`uvm_analysis_imp_decl(*)这个宏,可参考uvm source code.

读UVM源代码(六)TLM第1部分：analysis_port

class A extends uvm_component;
   `uvm_component_utils(A)
   uvm_analysis_port#(my_transaction) A_ap;
   function new(string name, uvm_component parent);
      super.new(name, parent);
   endfunction
   extern function void build_phase(uvm_phase phase);
   extern virtual  task main_phase(uvm_phase phase);
endclass
function void A::build_phase(uvm_phase phase);
   super.build_phase(phase);
   A_ap = new("A_ap", this);
endfunction
task A::main_phase(uvm_phase phase);
   my_transaction tr;
   repeat(10) begin
      #10;
      tr = new("tr");
      assert(tr.randomize());
      A_ap.write(tr);  //main_phase 中写
   end
endtask

class B extends uvm_component;
   `uvm_component_utils(B)
   uvm_analysis_imp#(my_transaction, B) B_imp;
   function new(string name, uvm_component parent);
      super.new(name, parent);
   endfunction
   extern function void build_phase(uvm_phase phase);
   extern function void connect_phase(uvm_phase phase);
   extern function void write(my_transaction tr);
   extern virtual  task main_phase(uvm_phase phase);
endclass
function void B::build_phase(uvm_phase phase);
   super.build_phase(phase);
   B_imp = new("B_imp", this);
endfunction
function void B::connect_phase(uvm_phase phase);
   super.connect_phase(phase);
endfunction
function void B::write(my_transaction tr);
   `uvm_info("B", "receive a transaction", UVM_LOW) 
   tr.print();
endfunction
task B::main_phase(uvm_phase phase);  //B的main_phase中不需要任何操作
endtask

uvm_tlm_analysi_fifo

• FIFO中的analysis_export和blocking_get_export虽然名字有export，单类型是imp；
• 使用uvm_tlm_analysi_fifo就不用写write函数
• fifo有两种：uvm_tlm_analysi_fifo和uvm_tlm_fifo;
• 两个fifo唯一差别：uvm_tlm_analysi_fifo有analysis_export 和 write函数，
• fifo本质上是个component

driver和sequencer为什么不用ap连接？？？