Quartus常见错误分析
| 1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list 2 Warning: Found pins ing as undefined clocks and/or memory enables 3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout. 4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen" 5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew 6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design. 7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list 8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register 9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND 10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details. 11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details. 12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out" 13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design. 14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component 15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge 16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]" 17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node. 18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND 19 Warning: Design contains 2 input pin(s) that do not drive logic 20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1" 21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or" 22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared 23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors 24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type 25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks 26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19) 27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge 28Error: Can't elaborate top-level user hierarchy 29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有两个以上赋值语句，不能确定“cs_in”的值， 30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design. 31 Error: Can't access JTAG chain |