曼彻斯特编码器的vhdl实现代码

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 entity manchester_encode is
     Port ( clk : in  STD_LOGIC;
            data_in : in  STD_LOGIC;
            data_out : out  STD_LOGIC);
 end manchester_encode;
 architecture Behavioral of manchester_encode is
 signal count:std_logic_vector(1 downto 0);
 type work_type is (init,working);
 signal work_st : work_type:=init;
 begin
 process (clk)
 begin
  if clk'event and clk='1' then
   if data_in='1' then
    count<="01";
   else
    count<="10";
   end if;
  end if;
 end process;
 process(clk)
 begin
    if clk'event and clk='1' then
       if work_st=working then
          data_out<=count(1);
          work_st<=init;
       else
          data_out<=count(0);
          work_st<=working;
       end if;
    end if;
  end process;

 end Behavioral;