VHDL细节笔记（含std_logic Libraries标准库的技术手册）
1. others=>'0'是什么意思？
q <= (others=>'0'); 表示将q的所有位赋值为0，当q位数较多时比较方便。。。
2. if (clk’event and clk=‘1’ )是什么意思？
信号属性函数：用来得到有关信号的行为功能信息;
信号‘event：当前的一个相当小的时间间隔内有信号事件发生,则返回’true’,否则返回‘false’;
3.关于conv_std_logic_vector 和 conv_integer 这两个函数的使用问题
全文来自于此：http://www.cs.sfu.ca/~ggbaker/reference/std_logic/
std_logic_arith
This is the library that defines some types and basic arithmetic operations for representing integers in standard ways. This is a Synopsys extention. The source code is in std_logic_arith. vhd and is freely redistributable.
The unsigned type
The signed type
The arithmetic functions: +, -,*
The comparison functions: <,<=, >, >=, =, /=
The shift functions: shl, shr
The conv_integer function
The conv_unsigned function
The conv_signed function
The conv_std_logic_vector function
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The conv_integer function
function conv_integer(arg:integer) return integer;
function conv_integer(arg: unsigned)return integer;
function conv_integer(arg: signed) return integer;
function conv_integer(arg: std_ulogic) return small_int;
These functions convert the arg argument to an integer.If the argument contains any undefined elements, a runtime warning is produced and 0 is returned.
The function provided by the std_logic_arith library can't convert a std_logic_vector to an integer because it is impossible to determine if it represents an unsigned or signed value. Functions that do this are included in the std_logic_unsigned and std_logic_signed libraries.
Examples
signal b : std_logic;
signal u1 :unsigned (3 downto 0);
signal s1 : signed (3 downto 0);
signali1, i2, i3 : integer;
...
u1 <= "1001";
s1 <="1001";
b <= 'X';
wait for 10 ns;
i1 <=conv_integer(u1); -- 9
i2 <=conv_integer(s1); -- -7
i3 <=conv_integer(b); -- warning produced in simulator
以上蓝字说明了一切(让我哭一会儿。。。百度你骗我。。。)
std_logic_arith不能将std_logic_vector转为integer，应该用std_logic_unsigned和std_logic_signed。。因为没法确定是有符号数还是无符号数。。。