基于VHDL语言、状态机的序列信号发生器的实现

一、实验平台

1、Basys3开发板；
2、Vivado2017.4开发环境；
3、VHDL语言。

二、实验描述

最近在学习时序电路，接触到状态机，就利用有限状态机，写了一个8位的序列信号发生器（11010010），分为串行输出和并行输出。这次只是仿真，所以没有进行分频，不过我会把后面的1HZ分频代码贴出来。

三、相关代码

1、主代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity signal_generate is
    Port (
           clk   : in STD_LOGIC;
           rst   : in STD_LOGIC;
           d     : out STD_LOGIC_VECTOR (7 downto 0);                       --并行输出
           d_out : out STD_LOGIC                                            --串行输出
          );
end signal_generate;

architecture Behavioral of signal_generate is
  type states is (s0,s1,s2,s3,s4,s5,s6,s7);
  signal state     : states:=s0;
  signal d1        : std_logic_vector(7 downto 0):="00000000";
  signal temp      : std_logic;
begin
--串并转换  
  process(clk)
  begin
    if(rst='1')then
      d1<="00000000";
    elsif(clk'event and clk='1')then              
      d1<=d1(6 downto 0)&temp;
    end if;
  end process;
 
----并行输出序列"11010010"
  process(clk)
    begin
      if(state=s0)then
        d<=d1;                     
      else
        d<=(others=>'0');
      end if;
    end process;
 
--状态转移进程 
  process(clk)
  begin
    if(rst='1')then
      state<=s0;
    elsif(clk'event and clk='1')then
      case state is
        when s0 =>
          state<=s1;
        when s1 =>
          state<=s2;
        when s2 =>
          state<=s3;
        when s3 =>
          state<=s4;
        when s4 =>
          state<=s5;
        when s5 =>
          state<=s6;
        when s6 =>
          state<=s7;
        when s7 =>
          state<=s0;
      end case;
    end if;
  end process;
  
--产生序列"11010010"
  process(state)
  begin
    case state is
      when s0 =>
        temp<='1';
      when s1 =>
        temp<='1';
      when s2 =>
        temp<='0';
      when s3 =>
        temp<='1';
      when s4 =>
        temp<='0';
      when s5 =>
        temp<='0';
      when s6 =>
        temp<='1';
      when s7 =>
        temp<='0';    
    end case;
  end process;
    
  d_out<=temp;
end Behavioral;

2、仿真文件(testbench)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity signal_generate_tb is
end signal_generate_tb;

architecture Behavioral of signal_generate_tb is
  component signal_generate
    Port (
           clk   : in STD_LOGIC;
           rst   : in STD_LOGIC;
           d     : out STD_LOGIC_VECTOR (7 downto 0);
           d_out : out STD_LOGIC
           );
  end component;
  
  signal clk   : std_logic:='0';
  signal rst   : std_logic:='0';
  signal d     : std_logic_vector(7 downto 0);
  signal d_out : std_logic;
  constant clk_period : time := 20 ns;
begin
  instant: signal_generate port map
    (clk=>clk,rst=>rst,d=>d,d_out=>d_out);

  clk_gen:process
  begin
    wait for clk_period/2;
    clk<='1';
    wait for clk_period/2;
    clk<='0';
  end process;
  
  rst_gen:process
  begin
    wait for 60 ns;
    rst<='1';
    wait for 10 ns;
    rst<='0';
    wait;           --一直等待
  end process;

end Behavioral;

3、分频相关代码

--clk=100MHZ,clk_f=1HZ
  count_gen:process(clk)
  begin
    if(clk'event and clk='1')then
      if(count=9)then
        count<=0;     
      else
        count<=count+1;        
      end if;
    end if;
  end process;
  
  clk_f_gen:process(clk)
  begin
    if(clk'event and clk='1')then
      if(count=0)then
        clk_f<=not clk_f;
      else
        clk_f<=clk_f;
      end if;
    end if;  
  end process;

三、仿真结果

其中，rst表示复位信号，高电平有效；state表示当前状态；d_out表示串行输出；d[7…0]表示并行输出。

以上就是今天写的一个关于状态机的小实验，如果有问题欢迎大家交流讨论。