[HDLBits] Module shift8

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside. (See also: mux9to1v)

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] w1,w2,w3;
    my_dff8 d1 (clk,d,w1);
    my_dff8 d2 (clk,w1,w2);
    my_dff8 d3 (clk,w2,w3);
    always@(*) begin
        case(sel)
            2'b00:	begin
                q=d;
            end
            2'b01:	begin
                q=w1;
            end
            2'b10:	begin
                q=w2;
            end
            2'b11:	begin
                q=w3;
            end
        endcase
    end

endmodule

这里也非常有意思，首先注意wire类型是多位的。然后这里第一次用case，可以看看。

我第一次写的版本是：

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
	wire [7:0] w1,w2,w3;
    my_dff8 d1 (clk,d,w1);
    my_dff8 d2 (clk,w1,w2);
    my_dff8 d3 (clk,w2,w3);
    always@(*) begin
        case(sel)
            2'b00:	begin
                assign q=d;
            end
            2'b01:	begin
                assign q=w1;
            end
            2'b10:	begin
                assign q=w2;
            end
            2'b11:	begin
                assign q=w3;
            end
        endcase
    end

endmodule

但assign不能用于寄存器类型，因为assign是连续赋值，假设assign q=d，那么每当d变化时，assign也会随之变化，即便后续不再赋值。寄存器类型的功能是赋值一次后，在下次赋值前，其值不再变化。因此不能用连续赋值语句。这里直接用类似c和python的语句q=d即可，这样就实现了单次赋值，后续q的值不随d变化。