uvm白皮书练习_ch2_ch223_加入objection机制

UVM中通过objection机制来控制验证平台的关闭。
在每个phase中，UVM会检查是否有objection被提起（raise_ objection），如果有，那么等待这个objection被撤销（drop_objection）后停止仿真；如果没有，则马上结束当前phase。

目前将drop_objection语句当成是finish函数的替代者，只是在drop_objection语句之前必须先调用raise_objection语句，raise_objection和drop_ objection总是成对出现。

raise_objection语句必须在main_phase中第一个消耗仿真时间（所谓仿真时间，是指$time函数打印出的时间。与之相对的还有实际仿真中所消耗的CPU时间，通常说一个测试用例的运行时间即指CPU时间

如$display语句是不消耗仿真时间的，这些语句可以放在raise_objection之前，但是类似@(posedge top.clk)等语句是要消耗仿真时间的。

dut.sv

module dut (
    clk,
    rst_n,
    rxd,
    rx_dv,
    txd,
    tx_en
);
    input clk    ;   
    input rst_n  ;   
    input [7:0]rxd    ; 
    input rx_dv  ;   
    output txd   ;  
    output tx_en ; 

reg [7:0]   txd;
reg         tx_en;  

always @(posedge clk) begin
    if(!rst_n)begin
        txd     <=  8'h00;
        tx_en   <=  1'b0;
    end
    else begin
        txd     <=  rxd;
        tx_en   <=  rx_dv;
    end
end
endmodule

TB

my_driver.sv

`ifndef MY_DRIVER_SV
`define MY_DRIVER_SV

class my_driver  extends uvm_driver;
    `uvm_component_utils(my_driver)  //加入factory机制
    function new(string name="my_driver",uvm_component parent =null);
        super.new(name,parent);
    endfunction //new()
    extern  virtual task main_phase(uvm_phase phase);//调用附近的代码
endclass //my_driver  extends uvm_driver

task my_driver::main_phase(uvm_phase phase);
    phase.raise_objection(this);//ch223加入objection机制
    top_tb.rxd      <= 8'b0;//初始值复位
    top_tb.rx_dv    <= 1'b0;
    while (!top_tb.rst_n) 
        @(posedge top_tb.clk);//等个时钟
  
    for(int i =0;i<25;i++)begin
        @(posedge top_tb.clk);//等个时钟
        top_tb.rxd <= i[7:0];
        // top_tb.rxd <= $urand_range(0.255);
        top_tb.rx_dv    <= 1'b1;
        `uvm_info("my_driver","data is driver",UVM_LOW);
    end
    @(posedge top_tb.clk);
    top_tb.rx_dv    <=  1'b0;
    phase.drop_objection(this);//ch223加入objection机制

endtask //my_driver::main_phase
`endif

top_tb.sv

`timescale 1ns/1ns
`include "uvm_macros.svh"

import uvm_pkg::*;
`include "my_driver.sv"

module top_tb ;
reg         clk     ;    //时钟
reg         rst_n   ;   //复位
reg [7:0]   rxd     ;   //接受数据
reg         rx_dv   ;   //接受数据
reg [7:0]   txd     ;   //发送数据
reg         tx_en   ;   //发送数据

dut my_dut(
.clk   (clk  ),
.rst_n (rst_n),
.rxd   (rxd  ),
.rx_dv (rx_dv),
.txd   (txd  ),
.tx_en (tx_en)
);

// initial begin
//     my_driver drv;
//     drv = new("drv",null);//传入数据
//     drv.main_phase(null);
//     $finish;
// end
initial begin
    run_test("my_driver");
end
/*时钟模块*/
initial begin
    clk = 0;
    forever begin
        #100ns clk = ~clk;
    end
end
/*复位模块*/
initial begin
    rst_n = 1'b0;
    #1000;
    rst_n = 1'b1;
end

/*fsdb*/
//initial begin
//    $fsdbDumpfile("verilog.fsdb");
//    $fsdbDumpvars(0);
//    $display("fsdbDumpfilrs is start at %d",$time);
//    // #1e7;
//    // $finish;
//end
endmodule

仿真结果

将发送激励改成了25次

fsdbDumpfilrs is start at                    0
UVM_INFO my_driver.sv(24) @ 13000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 15000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 17000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 19000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 21000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 23000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 25000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 27000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 29000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 31000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 33000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 35000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 37000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 39000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 41000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 43000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 45000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 47000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 49000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 51000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 53000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 55000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 57000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 59000: uvm_test_top [my_driver] data is driver
UVM_INFO my_driver.sv(24) @ 61000: uvm_test_top [my_driver] data is driver

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   26
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[my_driver]    25