关于WPWS、TPWS

这两日vivado的时序结果中出现了TPWS Slack为负值的情况，荡了一下相关资料，算是有了一个初步了解。

概念

pulse width指的是时钟clk的高电平宽度和低电平宽度。和时钟周期一样，时钟的pulse width也是一个很重要的参数，对于确保寄存器稳定输出非常关键。

When a pulse width violation occurs, it is due to an inappropriate clock definition (pulse width and period checks) or an inappropriate clock topology that induces too much skew (max_skew check). You must review the Xilinx FPGA data sheet of the target device to understand the operation range of the primitive where the violation occurs. In the case of a skew violation, you must simplify the clock tree or place the clock resources closer to the violating pins.

UG906 中Report Pulse Width章节的介绍如下，

其他