Verilog Code of Experiment 3.1.2 [CoC]

用超前进位算法的扩展算法XXXXXXXXXXX。

不是很难，但编写，调试，仿真，烧版，也够偶家这等菜鸟忙活一阵了哭

/**
 * file:    FullAdder.v
 * author:    LiHs
 * desc:    'FullAdder' module;
 */

// a tipical 1-bit full_adder in logical circuit;
// use as module A in experiemnt;
module FullAdder (A, B, Cin, S, G, P);    // port list;

input A, B, Cin;
output S, G, P;    // IO list;

assign S = A ^ B ^ Cin;
assign G = A & B;
assign P = A | B;

endmodule

-------------------------------------------------------------------------------

/**
 * file:    CarrayPass.v
 * author:    LiHs
 * desc:    'CarrayPass' module;
 */

// pass carry info to other modules;
// use as module B in experiemnt;
module CarryPass (p0, g0, C0_out, p1, g1, C1, P1_0, G1_0, C0_in);    // port list;

input p0, g0, p1, g1, C0_in;
output P1_0, G1_0, C1, C0_out;    // IO list;

assign C0_out = C0_in;
assign G1_0 = g1 | p1 & g0;
assign P1_0 = p1 & p0;
assign C1 = g0 | p0 & C0_in;

endmodule

-----------------------------------------------------------------------------

/**
 * file:    Adder4.v
 * author:    LiHs
 * desc:    'Adder4' module;
 */

// a 4-bit_adder using extended carry look ahead;
// use as top module in experiemnt;
module Adder4 (A, B, Cin, S, P, G);    // port list;
parameter n = 4;

input[n-1:0] A, B;
input Cin;
output[n-1:0] S;
output P, G;    // IO list;
wire[n-2:0] ModuleB_C0out;
wire[n-2:0] ModuleB_C1out;
wire[n-2:0] ModuleB_G1_0out;
wire[n-2:0] ModuleB_P1_0out;
wire[n-1:0] ModuleA_gout;
wire[n-1:0] ModuleA_pout;

    // module A 0;
    FullAdder fa0(.A(A[0]), .B(B[0]), .Cin(ModuleB_C0out[0]), .S(S[0]), .G(ModuleA_gout[0]), .P(ModuleA_pout[0]));

    // module A 1;
    FullAdder fa1(.A(A[1]), .B(B[1]), .Cin(ModuleB_C1out[0]), .S(S[1]), .G(ModuleA_gout[1]), .P(ModuleA_pout[1]));

    // module A 2;
    FullAdder fa2(.A(A[2]), .B(B[2]), .Cin(ModuleB_C0out[1]), .S(S[2]), .G(ModuleA_gout[2]), .P(ModuleA_pout[2]));

    // module A 3;
    FullAdder fa3(.A(A[3]), .B(B[3]), .Cin(ModuleB_C1out[1]), .S(S[3]), .G(ModuleA_gout[3]), .P(ModuleA_pout[3]));

    // module B 0;
    CarryPass cp0(.p0(ModuleA_pout[0]), .g0(ModuleA_gout[0]), .C0_out(ModuleB_C0out[0]),
        .p1(ModuleA_pout[1]), .g1(ModuleA_gout[1]), .C1(ModuleB_C1out[0]), .P1_0(ModuleB_P1_0out[0]),
        .G1_0(ModuleB_G1_0out[0]), .C0_in(ModuleB_C0out[2]));
        
    // module B 1;
    CarryPass cp1(.p0(ModuleA_pout[2]), .g0(ModuleA_gout[2]), .C0_out(ModuleB_C0out[1]),
        .p1(ModuleA_pout[3]), .g1(ModuleA_gout[3]), .C1(ModuleB_C1out[1]), .P1_0(ModuleB_P1_0out[1]),
        .G1_0(ModuleB_G1_0out[1]), .C0_in(ModuleB_C1out[2]));

    // module B 2;
    CarryPass cp2(.p0(ModuleB_P1_0out[0]), .g0(ModuleB_G1_0out[0]), .C0_out(ModuleB_C0out[2]),
        .p1(ModuleB_P1_0out[1]), .g1(ModuleB_G1_0out[1]), .C1(ModuleB_C1out[2]), .P1_0(P),
        .G1_0(G), .C0_in(Cin));

endmodule

RTL：

A simulatio：