VHDL——如何写简单的testbench
弄了好长时间vhdl，一直对testbench很迷惑。前几天静下心来好好看了下资料，终于会写简单的testbench了。
六进制计数器的代码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity cnt6 is
port
(clr,en,clk :in std_logic;
q :out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of cnt6 is
signal tmp :std_logic_vector(2 downto 0);
begin
process(clk)
-- variable q6:integer;
begin
if(clk'event and clk='1') then
if(clr='0')then
tmp<="000";
elsif(en='1') then
if(tmp="101")then
tmp<="000";
else
tmp<=unsigned(tmp)+'1';
end if;
end if;
end if;
q<=tmp;
-- qa<=q(0);
-- qb<=q(1);
-- qc<=q(2);
end process;
end rtl;
六进制计数器testbench的代码
library ieee;
use ieee.std_logic_1164.all;
entity cnt6_tb is
end cnt6_tb;
architecture rtl of cnt6_tb is
component cnt6
port(
clr,en,clk :in std_logic;
q :out std_logic_vector(2 downto 0)
);
end component;
signal clr :std_logic:='0';
signal en :std_logic:='0';
signal clk :std_logic:='0';
signal q :std_logic_vector(2 downto 0);
constant clk_period :time :=20 ns;
begin
instant:cnt6 port map
(
clk=>clk,en=>en,clr=>clr,q=>q
);
clk_gen:process
begin
wait for clk_period/2;
clk<='1';
wait for clk_period/2;
clk<='0';
end process;
clr_gen:process
begin
clr<='0';
wait for 30 ns;
clr<='1';
wait;
end process;
en_gen:process
begin
en<='0';
wait for 50ns;
en<='1';
wait;
end process;
end rtl;
其实testbench也有自己固定的一套格式，总结如下：
--测试平台文件(testbench)的基本结构
library ieee;
use ieee.std_logic_1164.all;
entity test_bench is --测试平台文件的空实体（不需要端口定义)
end test_bench;
architecture tb_behavior of test_bench is
component entity_under_test --被测试元件的声明
port(
list-of-ports-theri-types-and-modes
);
end component;
begin
instantiation:entity_under_test port map
(
port-associations
);
process() --产生时钟信号
……
end process;
process() --产生激励源
……
end process;
end tb_behavior;
-------------------------------------------------------------------
--简单计数程序源码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity sim_counter is
port(
clk :in std_logic;
reset :in std_logic;
count :out std_logic_vector(3 downto 0)
);
end entity;
architecture behavioral of sim_counter is
signal temp :std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='1' then
temp<="0000";
elsif clk'event and clk='1' then
temp<=temp+1;
end if;
end process;
count<=temp;
end behavioral;
-------------------------------------------------------------------
--简单计数程序，测试文件代码(testbench)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity counter_tb_vhd is --测试平台实体
end counter_tb_vhd;
architecture behavior of counter_tb_vhd is
--被测试元件（DUT）的声明
component sim_counter
port(
clk :in std_logic;
reset :in std_logic;
count :out std_logic_vector(3 downto 0)
);
end component;
--输入信号
signal clk:std_logic:='0';
signal reset :std_logic:='0';
--输出信号
signal count :std_logic_vector(3 downto 0);
constant clk_period :time :=20 ns; --时钟周期的定义
begin
dut:sim_counter port map(
clk=>clk,reset=>reset,counter=>counter
);
clk_gen:process
begin
clk='1';
wait for clk_period/2;
clk='0';
wait for clk_period/2;
end process;
tb:process --激励信号
begin
wait for 20 ns;
reset<='1';
wait for 20 ns;
reset<='0';
wait for 200 ns;
wait; --will wait forever;
end process;
end;
--激励信号的产生方式
--1.以一定的离散时间间隔产生激励信号的波形
--2.基于实体的状态产生激励信号，也就是说基于实体的输出响应产生激励信号
--两种常用的复位信号
--1.周期性的激励信号，如时钟
--2.时序变化的激励型号，如复位
--eg.产生不对称时钟信号
w_clk<='0' after period/4 when w_clk='1' else
'1' after 3*period/4 when w_clk='0' else
'0';
--eg.产生堆成时钟信号，process语句
clk_gen1:process
constan clk_period := 40 ns;
begin
clk='1';
wait for clk_period/2;
clk='0';
wait for clk_period/2;
end process;
如果自己不想写这些testbench的这些固定格式，可以在SIE里自动生成testbench文件的模板
步骤：New Surce -> VHDL Test Bench, 然后才会生成testbench
自动生成的testbench模板格式如下：
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "03/13/2011 20:05:04"
-- Vhdl Test Bench template for design : cnt6
--
-- Simulation tool : ModelSim (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY cnt6_vhd_tst IS
END cnt6_vhd_tst;
ARCHITECTURE cnt6_arch OF cnt6_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC;
SIGNAL clr : STD_LOGIC;
SIGNAL en : STD_LOGIC;
SIGNAL q : STD_LOGIC_VECTOR(2 DOWNTO 0);
COMPONENT cnt6
PORT (
clk : IN STD_LOGIC;
clr : IN STD_LOGIC;
en : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : cnt6
PORT MAP (
-- list connections between master ports and signals
clk => clk,
clr => clr,
en => en,
q => q
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END cnt6_arch;