【FPGA学习笔记】VHDL学习（六）用VHDL描述基本逻辑电路（时序逻辑电路：触发器，寄存器，计数器）

二、时序逻辑电路

时序逻辑电路时含有触发器的电路，有组合逻辑电路和存储电路组成。
输出不仅仅取决于输入，还取决于所处的状态。

锁存器采用电平信号控制，触发器采用电平信号控制。

1、普通寄存器—D触发器

--D触发器
LIBRARY IEEE;
USE IEE.STD_LOGIC_1164.ALL;
ENTITY reg IS
	PORT (clk : IN STD_LOGIC;
		    d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		    q : OUT STD_LOGIC_VECTOR(7 DOWN TO 0)
		);
END reg;

ARCHITECTURE art OF reg IS
BEGIN
	PROCESS(clk)
	BEGIN 
		IF(clk'EVENT AND clk = '1')THEN		
				q <= d;
		END IF;
	END PROCESS;
END art;

2、寄存器

D锁存器
当OE为0，G为1时，输出为D的值。

--D锁存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGN.ALL;
ENTITY latch_8 	IS
	PORT(OE : IN STD_LOGIC;
		 G  : IN STD_LOGIC;
		 D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 Q  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END latch_8;

ARCHITECTURE art OF latch_8 IS
	SIGNAL tmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
	PROCESS(OE,G,D)
	BEGIN
		IF OE = '0' THEN
			IF G = '1'THEN
				tmp <= D;
			END IF;
		ELSE
			tmp <= "ZZZZZZZZ"
		END IF;
		Q <= tmp;
	END PROCESS;
END art;

移位寄存器

--移位寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL

ENTITY shifter IS
	PORT( data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		  mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		  SHIFT_RIGHT,SHIFT_LEFT : IN STD_LOGIC;
		  clk : IN STD_LOGIC;
		  reset : IN STD_LOGIC;
		  Qout : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)  --Qout为buffer类型
		);
END shifter;

ARCHITECTURE art OF shifter IS

BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL(RISING_EDGE(clk));
		IF reset = '1' THEN
			Qout <= "ZZZZZZZZ";
		ELSE
			CASE mode IS
				WHEN "01"=>SHIFT_RIGHT&Qout(7 DOWNTO 0); --右移
				WHEN "10"=>Qout(6 DOWNTO 0)& SHIFT_LEFT; --左移
				WHEN "11"=>Qout <= data;                 --置数
				WHEN OTHERS => NULL;
			END CASE;
		END IF;
	END PROCESS;
END art;

计数器

1、同步计数器
在时钟脉冲驱动下，构成计数器的触发器统一动作。

--2进制同步计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL

ENTITY counter_12 IS
	POTR (clk, clr, en :IN STD_LOGIC;
		 Q1, Q2, Q3, Q4 ： OUT STD_LOGIC);
END counter_12;

ARCHITECTURE art OF counter_12 IS
	SIGNAL counter :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	Q1 <= counter(0);
	Q2 <= counter(1);
	Q3 <= counter(2);
	Q4 <= counter(3);
	PROCESS(clk,en,clr)
	BEGIN 
		IF clr = '0'THEN 
			counter <= "0000";
		ELSIF clk'EVENT AND clk = '1' THEN
			IF en = '1' THEN
				IF counter = "1011" THEN
					counter <= "0000";
				ELSE
					counter <= counter+1;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END art;

--模60的计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY counter_60 IS
	PORT (clk,clr : IN STD_LOGIC;
		Q1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		Q10 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END counter_60;

ARCHITECTURE art OF counter_60 IS
	SIGNAL tmp1 : STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL tmp10 : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	Q1 <= tmp1;
	Q10  <= tmp10;
	PROCESS (clk,clr)
	BEGIN
		IF (clr = '0')THEN
			tmp10 <= "0000";
			tmp1  <= "000";
		ELSIF (clk'EVENT AND clk = '1')THEN
			IF (tmp1 = '9')THEN
				tmp1 <= "0000"
				IF (tmp10 = '5')
					tmp10 <= "000";
				ELSE
					tmp10 <= tmp10 + 1;
				END IF;
			ELSE
				tmp1 <= tmp1 + 1;
			END IF;
		END IF;
	END PROCESS;
END art;

2、异步计数器
将各个触发器逐级串联，低级触发器的输出作为下一级触发器的时钟。

--异步加法计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DFFR IS                       --定义一个D触发器DFFR
	PORT(clk , clr, d : IN STD_LOGIC;
		Q ,BQ : OUT STD_LOGIC);
END DFFR;
ARCHITECTURE art OF DFFR IS
	SIGNAL Q_IN :STD_LOGIC;
BEGIN
	Q <= Q_IN;
	BQ <= NOT Q_IN;
	PROCESS(clk,clr)
	BEGIN
		IF (clr = '1')THEN
			Q_IN <= '0';
		ELSIF (clk'EVENT AND clK = '1')
			Q_IN <= d;
		END IF;
	END PROCESS;
END art;

ENTITY rplcounter IS
	PORT(clK,clr : IN STD_LOGIC;
		count ：OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rplcounter;
ARCHITECTURE art1 OF DFFR IS
	SIGNAL COUNT_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
	COMPONENT DFFR                        --说明元件
		PORT(clk , clr, d : IN STD_LOGIC;
		Q ,BQ : OUT STD_LOGIC);
	END COMPONENT;
BEGIN
	COUNT_IN(0) <= clK;
	GEN1: FOR i IN 0 TO 3 GENERATE--元件例化并定义引脚连接：低位触发器的输出作为下一级的时钟信号
		U:DFFR PORT MAP
		(clK => COUNT_IN(i);
		 clr => clr;
		 d => COUNT_IN(i+1);
		 Q => COUNT_IN(i);
		 BQ => COUNT_IN(i+1));
	END GENERATE;
END art1;