VHDL八位全加器的设计

VHDL编程语言八位全加器的设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADDER4B IS
PORT ( CIN4 : IN STD_LOGIC;
A4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT4 : OUT STD_LOGIC);
END ADDER4B;

ARCHITECTURE behav OF ADDER4B IS
SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL AA,BB : STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
AA<=‘0’&A4;
BB<=‘0’&B4;
SINT <= AA + BB + CIN4;
S4 <= SINT(3 DOWNTO 0);
COUT4 <= SINT(4);
END behav;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADDER8B IS
PORT ( CIN : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT : OUT STD_LOGIC );
END ADDER8B;

ARCHITECTURE struc OF ADDER8B IS
COMPONENT ADDER4B
PORT ( CIN4 : IN STD_LOGIC;
A4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT4 : OUT STD_LOGIC );
END COMPONENT;
SIGNAL CARRY_OUT : STD_LOGIC;
BEGIN
U1 : ADDER4B
PORT MAP ( CIN4 => CIN, A4 => A(3 DOWNTO 0),
B4 => B(3 DOWNTO 0), S4 => S(3 DOWNTO 0),COUT4 => CARRY_OUT );

    U2 : ADDER4B                    
       PORT MAP ( CIN4 => CARRY_OUT, A4 => A(7 DOWNTO 4),
       B4 => B(7 DOWNTO 4), S4 => S(7 DOWNTO 4),COUT4 => COUT );

END struc;