HDLBits刷题合集—21 Finding bugs in code

HDLBits刷题合集—21 Finding bugs in code

HDLBits-160 Bugs mux2

代码如下：

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out = sel ? a : b;

endmodule

HDLBits-161 Bugs nand3

代码如下：

module top_module (
	input a,
	input b, 
	input c, 
	output out);//
	
	wire outb;
    
    andgate inst1 ( .a(a), .b(b), .c(c), .d(1'b1), .e(1'b1), .out(outb) );
    assign out = ~ outb;
    
endmodule

HDLBits-162 Bugs mux4

代码如下

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux0, mux1;
    
    mux2 mux00 ( sel[0],    a,    b, mux0 );
    mux2 mux01 ( sel[0],    c,    d, mux1 );
    mux2 mux02 ( sel[1], mux0, mux1,  out );

endmodule

HDLBits-163 Bugs addsubz

代码如下：

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a + b;
          1: out = a - b;
    default: out = a + b;
        endcase
       if (|out)
   			result_is_zero = 0;
        else
        	result_is_zero = 1;
    end
   
endmodule

HDLBits-164 Bugs case

代码如下：

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid);

     always @(*)
        case (code)
            8'h45: begin
                valid = 1;
                  out = 0;
            end
            8'h16: begin
                valid = 1;
                  out = 1;
            end
            8'h1e: begin
                valid = 1;
                  out = 2;
            end
            8'h26: begin
                valid = 1;
                  out = 3;
            end
            8'h25: begin
                valid = 1;
                  out = 4;
            end
            8'h2e: begin
                valid = 1;
                  out = 5;
            end
            8'h36: begin
                valid = 1;
                  out = 6;
            end
            8'h3d: begin
               valid = 1;
                 out = 7;
            end
            8'h3e: begin
               valid = 1;
                 out = 8;
            end
            8'h46: begin
               valid = 1;
                 out = 9;
            end
            default: begin
               valid = 0;
                 out = 0;
            end
        endcase

endmodule

Note
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